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PIC18F45J10 Family Data Sheet
28/40/44-Pin High-Performance, RISC Microcontrollers
(c) 2009 Microchip Technology Inc.
DS39682E
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
28/40/44-Pin High-Performance, RISC Microcontrollers
Special Microcontroller Features:
* * * * * * * Operating Voltage Range: 2.0V to 3.6V 5.5V Tolerant Input (digital pins only) On-Chip 2.5V Regulator 4x Phase Lock Loop (PLL) available for Crystal and Internal Oscillators Self-Programmable under Software Control Low-Power, High-Speed CMOS Flash Technology C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code Priority Levels for Interrupts 8 x 8 Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s Single-Supply In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins In-Circuit Debug (ICD) with Three Breakpoints via Two Pins Power-Managed modes with Clock Switching: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off
Peripheral Highlights:
* High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) * Three Programmable External Interrupts * Four Input Change Interrupts * One Capture/Compare/PWM (CCP) module * One Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart * Two Master Synchronous Serial Port (MSSP) modules supporting 3-Wire SPI (all 4 modes) and I2CTM Master and Slave modes * One Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect (ABD) * 10-Bit, up to 13-Channel Analog-to-Digital Converter module (A/D): - Auto-acquisition capability - Conversion available during Sleep - Self-calibration feature * Dual Analog Comparators with Input Multiplexing
* * * * * *
Flexible Oscillator Structure:
* * * * * * Two Crystal modes, up to 40 MHz Two External Clock modes, up to 40 MHz Internal 31 kHz Oscillator Secondary Oscillator using Timer1 @ 32 kHz Two-Speed Oscillator Start-up Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops
Program Memory Device SRAM Data Flash # Single-Word Memory (bytes) (bytes) Instructions 16K 32K 16K 32K 8192 16384 8192 16384 1024 1024 1024 1024 I/O
EUSART
MSSP 10-Bit A/D (ch) CCP/ ECCP (PWM) 2/0 2/0 1/1 1/1 1 1 2 2 SPI Y Y Y Y Master I2CTM Y Y Y Y
Comparators 2 2 2 2
PIC18F24J10 PIC18F25J10 PIC18F44J10 PIC18F45J10
21 21 32 32
10 10 13 13
1 1 1 1
(c) 2009 Microchip Technology Inc.
DS39682E-page 1
Timers 8/16-Bit 1/2 1/2 1/2 1/2
PIC18F45J10 FAMILY
Pin Diagrams
28-Pin SPDIP, SOIC, SSOP (300 MIL)
MCLR RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ VDDCORE/VCAP RA5/AN4/SS1/C2OUT VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK1/SCL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
= Pins are up to 5.5V tolerant
RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/T0CKI/C1OUT RB4/KBI0/AN11 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1
* Pin feature is dependent on device configuration. .
28-Pin QFN
RA1/AN1 RA0/AN0 MCLR RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/T0CKI/C1OUT RB4/KBI0/AN11
PIC18F24J10 PIC18F25J10
= Pins are up to 5.5V tolerant
28 27 26 25 24 23 22 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ VDDCORE/VCAP RA5/AN4/SS1/C2OUT VSS OSC1/CLKI OSC2/CLKO 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT
PIC18F24J10 PIC18F25J10
8 9 10 11 12 13 14
* Pin feature is dependent on device configuration.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK1/SCL1 RC4/SDI1/SDA1 RC5/SDO1 RC6/TX/CK
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(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
Pin Diagrams (Continued)
40-Pin PDIP (600 MIL)
MCLR RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ VDDCORE/VCAP RA5/AN4/SS1/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK1/SCL1 RD0/PSP0/SCK2/SCL2 RD1/PSP1/SDI2/SDA2 * Pin feature is dependent on device configuration. .
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
= Pins are up to 5.5V tolerant
40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23 22 21
RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/T0CKI/C1OUT RB4/KBI0/AN11 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 RD3/PSP3/SS2 RD2/PSP2/SDO2
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 RD3/PSP3/SS2 RD2/PSP2/SDO2 RD1/PSP1/SDI2/SDA2 RD0/PSP0/SCK2/SCL2 RC3/SCK1/SCL1 RC2/CCP1/P1A RC1/T1OSI/CCP2* RC0/T1OSO/T1CKI
44-Pin QFN(1)
PIC18F44J10 PIC18F45J10
= Pins are up to 5.5V tolerant
* Pin feature is dependent on device configuration. Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
(c) 2009 Microchip Technology Inc.
RB3/AN9/CCP2* NC RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC RB7/KBI3/PGD MCLR RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREFRA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8
1 2 3 4 5 6 7 8 9 10 11
PIC18F44J10 PIC18F45J10
33 32 31 30 29 28 27 26 25 24 23
OSC2/CLKO OSC1/CLKI VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS1/C2OUT VDDCORE/VCAP
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PIC18F45J10 FAMILY
Pin Diagrams (Continued)
44-Pin TQFP
RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 RD3/PSP3/SS2 RD2/PSP2/SDO2 RD1/PSP1/SDI2/SDA2 RD0/PSP0/SCK2/SCL2 RC3/SCK1/SCL1 RC2/CCP1/P1A RC1/T1OSI/CCP2* NC
= Pins are up to 5.5V tolerant
44 43 42 41 40 39 38 37 36 35 34
* Pin feature is dependent on device configuration.
NC NC RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC RB7/KBI3/PGD MCLR RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREFRA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2*
1 2 3 4 5 6 7 8 9 10 11
PIC18F44J10 PIC18F45J10
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKO OSC1/CLKI VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS1/C2OUT VDDCORE/VCAP
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(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 23 3.0 Oscillator Configurations ............................................................................................................................................................ 27 4.0 Power-Managed Modes ............................................................................................................................................................. 35 5.0 Reset .......................................................................................................................................................................................... 41 6.0 Memory Organization ................................................................................................................................................................. 51 7.0 Flash Program Memory.............................................................................................................................................................. 71 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 81 9.0 Interrupts .................................................................................................................................................................................... 83 10.0 I/O Ports ..................................................................................................................................................................................... 97 11.0 Timer0 Module ......................................................................................................................................................................... 115 12.0 Timer1 Module ......................................................................................................................................................................... 119 13.0 Timer2 Module ......................................................................................................................................................................... 125 14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 127 15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 135 16.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 149 17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 193 18.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 215 19.0 Comparator Module.................................................................................................................................................................. 225 20.0 Comparator Voltage Reference Module................................................................................................................................... 231 21.0 Special Features of the CPU.................................................................................................................................................... 235 22.0 Instruction Set Summary .......................................................................................................................................................... 249 23.0 Development Support............................................................................................................................................................... 299 24.0 Electrical Characteristics .......................................................................................................................................................... 303 25.0 Packaging Information.............................................................................................................................................................. 337 Appendix A: Revision History............................................................................................................................................................. 349 Appendix B: Migration Between High-End Device Families............................................................................................................... 350 Index .................................................................................................................................................................................................. 353 The Microchip Web Site ..................................................................................................................................................................... 363 Customer Change Notification Service .............................................................................................................................................. 363 Customer Support .............................................................................................................................................................................. 363 Reader Response .............................................................................................................................................................................. 364 PIC18F45J10 family Product Identification System ........................................................................................................................... 365
(c) 2009 Microchip Technology Inc.
DS39682E-page 5
PIC18F45J10 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS39682E-page 6
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
1.0 DEVICE OVERVIEW
1.1.2
This document contains device specific information for the following devices: * PIC18F24J10 * PIC18F25J10 * PIC18F44J10 * PIC18F45J10 * PIC18LF24J10 * PIC18LF25J10 * PIC18LF44J10 * PIC18LF45J10
MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F45J10 family offer three different oscillator options. These include: * Two Crystal modes, using crystals or ceramic resonators * Two External Clock modes * INTRC source (approximately 31 kHz) Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.
This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price. The PIC18F45J10 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.
1.1
1.1.1
Core Features
LOW POWER
All of the devices in the PIC18F45J10 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-Fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 24.0 "Electrical Characteristics" for values.
(c) 2009 Microchip Technology Inc.
DS39682E-page 7
PIC18F45J10 FAMILY
1.2 Other Special Features 1.3
* Communications: The PIC18F45J10 family incorporates a range of serial communication peripherals, including 1 independent Enhanced USART and 2 Master SSP modules capable of both SPI and I2C (Master and Slave) modes of operation. Also, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications. * Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18F45J10 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. * Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions and Auto-Restart, to reactivate outputs once the condition has cleared. * Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN/J2602 protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. * 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 24.0 "Electrical Characteristics" for time-out periods.
Details on Individual Family Members
Devices in the PIC18F45J10 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (16 Kbytes for PIC18F24J10/44J10 devices and 32 Kbytes for PIC18F25J10/45J10). A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). CCP and Enhanced CCP implementation (28-pin devices have 2 standard CCP modules, 40/44-pin devices have one standard CCP module and one ECCP module). Parallel Slave Port (present only on 40/44-pin devices). One MSSP module for PIC18F24J10/25J10 devices and 2 MSSP modules for PIC18F44J10/45J10 devices Parts designated with an "F" part number (i.e., PIC18F25J10) have a minimum VDD of 2.7 volts, whereas parts designated with an "LF" part number (i.e., PIC18LF25J10) can operate between 2.0-3.6 volts on VDD; however, VDDCORE should never exceed VDD.
2. 3. 4.
5. 6.
7.
All of the other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. The PIC18F45J10 family of devices provides an on-chip voltage regulator to supply the correct voltage levels to the core. Parts designated with an "F" part number (such as PIC18F25J10) have the voltage regulator enabled. These parts can run from 2.7-3.6 volts on VDD but should have the VDDCORE pin connected to VSS through a lowESR capacitor. Parts designated with an "LF" part number (such as PIC18LF24J10) do not enable the voltage regulator. An external supply of 2.0-2.7 Volts has to be supplied to the VDDCORE pin while 2.0-3.6 Volts can be supplied to VDD (VDDCORE should never exceed VDD). See Section 21.3 "On-Chip Voltage Regulator" for more details about the internal voltage regulator.
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(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-1: DEVICE FEATURES
PIC18F24J10 DC - 40 MHz 16384 8192 1024 19 Ports A, B, C 3 2 0 MSSP, Enhanced USART No 10 Input Channels POR, BOR(1), RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR, WDT Yes 75 Instructions; 83 with Extended Instruction Set enabled 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC18F25J10 DC - 40 MHz 32768 16384 1024 19 Ports A, B, C 3 2 0 MSSP, Enhanced USART No 10 Input Channels POR, BOR(1), RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR, WDT Yes 75 Instructions; 83 with Extended Instruction Set enabled 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC18F44J10 DC - 40 MHz 16384 8192 1024 20 Ports A, B, C, D, E 3 1 1 MSSP, Enhanced USART Yes 13 Input Channels POR, BOR(1), RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR, WDT Yes 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP PIC18F45J10 DC - 40 MHz 32768 16384 1024 20 Ports A, B, C, D, E 3 1 1 MSSP, Enhanced USART Yes 13 Input Channels POR, BOR(1), RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR, WDT Yes 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PSP) 10-Bit Analog-to-Digital Module Resets (and Delays)
Programmable Brown-out Reset Instruction Set
Packages
Note 1:
BOR is not available in PIC18LF2XJ10/4XJ10 devices.
(c) 2009 Microchip Technology Inc.
DS39682E-page 9
PIC18F45J10 FAMILY
FIGURE 1-1:
Table Pointer<21> inc/dec logic 21 20 8
PCLATU PCLATH
PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (1 Kbyte) Address Latch 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC RB7/KBI3/PGD
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA5/AN4/SS1/C2OUT
PCU PCH PCL Program Counter 31 Level Stack
Address Latch Program Memory (16/32 Kbytes) Data Latch 8 STKPTR
Table Latch
ROM Latch
Instruction Bus <16> IR
Address Decode
Instruction Decode and Control
State Machine Control Signals
8
PRODH PRODL 3 BITOP 8 8 x 8 Multiply 8 W 8 8 ALU<8> 8 8 8
PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK1/SCL1 RC4/SDI1/SDA1 RC5/SDO1 RC6/TX/CK RC7/RX/DT
VDDCORE OSC1 OSC2 T1OSI T1OSO MCLR VDD, VSS
Internal Oscillator Block INTRC Oscillator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer
Single-Supply Programming In-Circuit Debugger
Brown-out(2) Reset Fail-Safe Clock Monitor
Precision Band Gap Reference
BOR(2)
Timer0
Timer1
Timer2
ADC 10-Bit
Comparator
CCP1
CCP2
MSSP
EUSART
Note
1: 2:
CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
DS39682E-page 10
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 1-2:
Table Pointer<21> inc/dec logic 21 20 8
PCLATU PCLATH
PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (3.9 Kbytes) Address Latch 12 Data Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA5/AN4/SS1/C2OUT
8
PCU PCH PCL Program Counter 31 Level Stack
PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC RB7/KBI3/PGD
Address Latch Program Memory (16/32 Kbytes) Data Latch 8 STKPTR
Table Latch
ROM Latch
Instruction Bus <16>
IR
Address Decode
PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK1/SCL1 RC4/SDI1/SDA1 RC5/SDO1 RC6/TX/CK RC7/RX/DT
Instruction Decode and Control
State Machine Control Signals
8
PRODH PRODL 3 BITOP 8 8 x 8 Multiply 8 W 8 8 ALU<8> 8 PORTE Precision Band Gap Reference RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 8 8 PORTD RD0/PSP0/SCK2/SCL2 RD1/PSP1/SDI2/SDA2 RD2/PSP2/SDO2 RD3/PSP3/SS2 RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D
VDDCORE OSC1 OSC2 T1OSI T1OSO MCLR VDD, VSS
Internal Oscillator Block INTRC Oscillator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer
Single-Supply Programming In-Circuit Debugger
Brown-out Reset Fail-Safe Clock Monitor
(2)
BOR(2)
Timer0
Timer1
Timer2
ADC 10-Bit
Comparator
ECCP1
CCP2
MSSP
EUSART
Note
1: 2:
CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
(c) 2009 Microchip Technology Inc.
DS39682E-page 11
PIC18F45J10 FAMILY
TABLE 1-2:
Pin Name
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS
Pin Number Pin Buffer SPDIP, SOIC, QFN Type Type SSOP 1 26 I 9 6 I I 10 7 O O -- -- -- CMOS ST Description
MCLR MCLR OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 CLKO
Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. See related OSC2/CLKO pins. Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In EC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. CMOS = CMOS compatible input or output I = Input P = Power
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39682E-page 12
(c) 2009 Microchip Technology Inc.
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TABLE 1-2:
Pin Name
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer SPDIP, SOIC, QFN Type Type SSOP 2 27 I/O TTL I Analog 3 28 I/O TTL I Analog 4 1 I/O TTL I Analog I Analog O Analog 5 2 I/O TTL I Analog I Analog 7 4 I/O TTL I Analog I TTL O -- Digital I/O. Analog Input 4. SPI slave select input. Comparator 2 output. CMOS = CMOS compatible input or output I = Input P = Power Digital I/O. Analog Input 3. A/D reference voltage (high) input. Digital I/O. Analog Input 2. A/D reference voltage (low) input. Comparator reference voltage output. Digital I/O. Analog Input 1. Digital I/O. Analog Input 0. Description
PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA5/AN4/SS1/C2OUT RA5 AN4 SS1 C2OUT
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
(c) 2009 Microchip Technology Inc.
DS39682E-page 13
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TABLE 1-2:
Pin Name
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer SPDIP, SOIC, QFN Type Type SSOP Description
PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 RB1 INT1 AN10 RB2/INT2/AN8 RB2 INT2 AN8 RB3/AN9/CCP2 RB3 AN9 CCP2(1) RB4/KBI0/AN11 RB4 KBI0 AN11 RB5/KBI1/T0CKI/ C1OUT RB5 KBI1 T0CKI C1OUT RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD 21 18 I/O TTL I ST I ST I Analog 22 19 I/O TTL I ST I Analog 23 20 I/O TTL I ST I Analog 24 21 I/O TTL I Analog I/O ST 25 22 I/O TTL I TTL I Analog 26 23 I/O I I O 27 24 I/O I I/O 28 25 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. TTL TTL ST -- Digital I/O. Interrupt-on-change pin. Timer0 external clock input. Comparator 1 output. Digital I/O. Interrupt-on-change pin. Analog Input 11. Digital I/O. Analog Input 9. Capture 2 input/Compare 2 output/PWM2 output. Digital I/O. External Interrupt 2. Analog input 8. Digital I/O. External Interrupt 1. Analog input 10. Digital I/O. External Interrupt 0. PWM Fault input for CCP1. Analog input 12.
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39682E-page 14
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-2:
Pin Name
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer SPDIP, SOIC, QFN Type Type SSOP 11 8 I/O O I 12 9 I/O ST I Analog I/O ST 13 10 I/O I/O 14 11 I/O I/O I/O 15 12 I/O I I/O 16 13 I/O O 17 14 I/O O I/O 18 15 I/O I I/O 8, 19 20 6 5, 16 17 3 P P -- -- Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power P P ST ST ST -- -- Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. ST -- ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). ST -- Digital I/O. SPI data out. ST ST ST Digital I/O. SPI data in. I2C data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. Description
PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) RC2/CCP1 RC2 CCP1 RC3/SCK1/SCL1 RC3 SCK1 SCL1 RC4/SDI1/SDA1 RC4 SDI1 SDA1 RC5/SDO1 RC5 SDO1 RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT VSS VDD VDDCORE/VCAP VDDCORE VCAP
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
(c) 2009 Microchip Technology Inc.
DS39682E-page 15
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name MCLR MCLR OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 CLKO
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS
Pin Number PDIP 1 18 Pin Buffer QFN TQFP Type Type 18 I 13 32 30 I I 14 33 31 O O -- -- -- CMOS ST Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. See related OSC2/CLKO pins. Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. CMOS = CMOS compatible input or output I = Input P = Power
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39682E-page 16
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP 2 Pin Buffer QFN TQFP Type Type 19 19 I/O I 3 20 20 I/O I 4 21 21 I/O I I O 5 22 22 I/O I I 7 24 24 I/O I I O TTL Analog TTL -- Digital I/O. Analog Input 4. SPI slave select input. Comparator 2 output. TTL Analog Analog Digital I/O. Analog Input 3. A/D reference voltage (high) input. TTL Analog Analog Analog Digital I/O. Analog Input 2. A/D reference voltage (low) input. Comparator reference voltage output. TTL Analog Digital I/O. Analog Input 1. TTL Analog Digital I/O. Analog Input 0. Description PORTA is a bidirectional I/O port.
RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA5/AN4/SS1/C2OUT RA5 AN4 SS1 C2OUT
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
CMOS = CMOS compatible input or output I = Input P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
(c) 2009 Microchip Technology Inc.
DS39682E-page 17
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 RB1 INT1 AN10 RB2/INT2/AN8 RB2 INT2 AN8 RB3/AN9/CCP2 RB3 AN9 CCP2(1) RB4/KBI0/AN11 RB4 KBI0 AN11 RB5/KBI1/C1OUT RB5 KBI1 C1OUT RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD
33
9
8 I/O I I I TTL ST ST Analog TTL ST Analog TTL ST Analog TTL Analog ST TTL TTL Analog TTL TTL -- TTL TTL ST Digital I/O. External Interrupt 0. PWM Fault input for Enhanced CCP1. Analog input 12. Digital I/O. External Interrupt 1. Analog input 10. Digital I/O. External Interrupt 2. Analog input 8. Digital I/O. Analog Input 9. Capture 2 input/Compare 2 output/PWM2 output. Digital I/O. Interrupt-on-change pin. Analog Input 11. Digital I/O. Interrupt-on-change pin. Comparator 1 output. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power
34
10
9 I/O I I
35
11
10 I/O I I
36
12
11 I/O I I/O
37
14
14 I/O I I
38
15
15 I/O I O
39
16
16 I/O I I/O
40
17
17 I/O I I/O TTL TTL ST
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39682E-page 18
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP 15 Pin Buffer QFN TQFP Type Type 34 32 I/O O I 16 35 35 I/O I I/O 17 36 36 I/O I/O O 18 37 37 I/O I/O I/O 23 42 42 I/O I I/O 24 43 43 I/O O 25 44 44 I/O O I/O 26 1 1 I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). CMOS = CMOS compatible input or output I = Input P = Power ST -- ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). ST -- Digital I/O. SPI data out. ST ST ST Digital I/O. SPI data in. I2C data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. ST ST -- Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Enhanced CCP1 output. ST CMOS ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ST -- ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. Description PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) RC2/CCP1/P1A RC2 CCP1 P1A RC3/SCK1/SCL1 RC3 SCK1 SCL1 RC4/SDI1/SDA1 RC4 SDI1 SDA1 RC5/SDO1 RC5 SDO1 RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
(c) 2009 Microchip Technology Inc.
DS39682E-page 19
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.
RD0/PSP0/SCK2/ SCL2 RD0 PSP0 SCK2 SCL2 RD1/PSP1/SDI2/SDA2 RD1 PSP1 SDI2 SDA2 RD2/PSP2/SDO2 RD2 PSP2 SDO2 RD3/PSP3/SS2 RD3 PSP3 SS2 RD4/PSP4 RD4 PSP4 RD5/PSP5/P1B RD5 PSP5 P1B RD6/PSP6/P1C RD6 PSP6 P1C RD7/PSP7/P1D RD7 PSP7 P1D
19
38
38 I/O I/O I/O I/O ST TTL ST ST Digital I/O. Parallel Slave Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. Digital I/O. Parallel Slave Port data. SPI data in. I2C data I/O. Digital I/O. Parallel Slave Port data. SPI data out. Digital I/O. Parallel Slave Port data. SPI slave select input. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input P = Power
20
39
39 I/O I/O I I/O ST TTL ST ST ST TTL -- ST TTL TTL ST TTL ST TTL -- ST TTL -- ST TTL --
21
40
40 I/O I/O O
22
41
41 I/O I/O I
27
2
2 I/O I/O
28
3
3 I/O I/O O
29
4
4 I/O I/O O
30
5
5 I/O I/O O
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39682E-page 20
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP 8 Pin Buffer QFN TQFP Type Type 25 25 I/O I I 9 26 26 I/O I I 10 27 27 I/O I I 12, 31 6, 30, 31 11, 32 6 6, 29 P P ST TTL Analog -- -- Digital I/O. Chip Select control for Parallel Slave Port (see related RD and WR pins). Analog input 7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. ST TTL Analog Digital I/O. Write control for Parallel Slave Port (see CS and RD pins). Analog input 6. ST TTL Analog Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog input 5. Description PORTE is a bidirectional I/O port.
RE0/RD/AN5 RE0 RD AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS AN7 VSS VDD VDDCORE/VCAP VDDCORE VCAP NC
7, 8, 7, 28 28, 29 23 23
P P -- 13 12, 13, 33, 34 --
-- -- --
Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. No connect. CMOS = CMOS compatible input or output I = Input P = Power
Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
(c) 2009 Microchip Technology Inc.
DS39682E-page 21
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NOTES:
DS39682E-page 22
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS
Basic Connection Requirements
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
C2(2)
2.1
VDD
VDD
Getting started with the PIC18F45J10 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") * ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.4 "Voltage Regulator Pins (VCAP/VDDCORE)") These pins must also be connected if they are being used in the end application: * PGC/PGD pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used.
R1 R2
MCLR
VSS
(1) (1)
ENVREG VCAP/VDDCORE
C1 PIC18FXXJXX
VSS VDD
C7
C6(2)
AVDD VDD VSS AVSS VDD VSS
C3(2)
C5(2)
C4(2)
Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 k R2: 100 to 470 Note 1: See Section 2.4 "Voltage Regulator Pins (VCAP/VDDCORE)" for explanation of ENVREG pin connections. The example shown is for a PIC18FJ device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.
2:
The minimum mandatory connections are shown in Figure 2-1.
(c) 2009 Microchip Technology Inc.
DS39682E-page 23
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2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
2.3
Master Clear (MCLR) Pin
The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.
The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
VDD R1
EXAMPLE OF MCLR PIN CONNECTIONS
R2 JP C1
MCLR PIC18FXXJXX
2.2.2
TANK CAPACITORS
Note 1:
On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F.
R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.
2:
DS39682E-page 24
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
2.4 Voltage Regulator Pins (VCAP/VDDCORE) 2.5 ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGC/PGD pins) programmed into the device matches the physical connections for the ICSP to the MPLAB(R) ICD 2, MPLAB ICD 3 or REAL ICETM emulator. For more information on the ICD 2, ICD 3 and REAL ICE emulator connection requirements, refer to the following documents that are available on the Microchip web site. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" (DS51331) * "Using MPLAB(R) ICD 2" (poster) (DS51265) * "MPLAB(R) ICD 2 Design Advisory" (DS51566) * "Using MPLAB(R) ICD 3" (poster) (DS51765) * "MPLAB(R) ICD 3 Design Advisory" (DS51764) * "MPLAB(R) REAL ICETM In-Circuit Emulator User's Guide" (DS51616) * "Using MPLAB(R) REAL ICETM In-Circuit Emulator" (poster) (DS51749)
When the regulator is enabled (F devices), a low-ESR (<5) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor (10 F typical) connected to ground. The type can be ceramic or tantalum. A suitable example is the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or equivalent. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 24.0 "Electrical Characteristics" for additional information. When the regulator is disabled (LF devices), the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section 24.0 "Electrical Characteristics" for information on VDD and VDDCORE.
FIGURE 2-3:
FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP
10
1 ESR ()
0.1
0.01
0.001
0.01
0.1
1 10 100 Frequency (MHz)
1000 10,000
Note:
Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25C, 0V DC bias.
(c) 2009 Microchip Technology Inc.
DS39682E-page 25
PIC18F45J10 FAMILY
2.6 External Oscillator Pins
FIGURE 2-4:
Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 "Oscillator Configurations" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-4. For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work"
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Main Oscillator 13 Guard Ring Guard Trace Secondary Oscillator 14 15 16 17 18 19 20
2.7
Unused I/Os
Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low.
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3.0
3.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 3-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION)
OSC1 To Internal Logic Sleep
The PIC18F45J10 family of devices can be operated in five different oscillator modes: 1. 2. 3. 4. 5. HS High-Speed Crystal/Resonator HSPLL High-Speed Crystal/Resonator with Software PLL Control EC External Clock with FOSC/4 Output ECPLL External Clock with Software PLL Control INTRC Internal 31 kHz Oscillator
C1(1)
XTAL
OSC2 C2(1) Note 1: 2: 3: RS(2)
RF(3)
PIC18F45J10
Four of these are selected by the user by programming the FOSC<2:0> Configuration bits. The fifth mode (INTRC) may be invoked under software control; it can also be configured as the default mode on device Resets.
See Table 3-1 and Table 3-2 for initial values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the oscillator mode chosen.
3.2
Crystal Oscillator/Ceramic Resonators (HS Modes)
TABLE 3-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications.
Typical Capacitor Values Used: Mode HS Freq. 8.0 MHz 16.0 MHz OSC1 27 pF 22 pF OSC2 27 pF 22 pF
Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 3-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz
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TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq. 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 HS 27 pF 22 pF 15 pF C2 27 pF 22 pF 15 pF
3.3
External Clock Input (EC Modes)
Osc Type
The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-2 shows the pin connections for the EC Oscillator mode.
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 4 MHz 8 MHz 20 MHz
FIGURE 3-2:
EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)
Clock from Ext. System FOSC/4
OSC1/CLKI
PIC18F45J10
OSC2/CLKO
An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-3. In this configuration, the divide-by-4 output on OSC2 is not available.
Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
FIGURE 3-3:
EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
Clock from Ext. System Open
OSC1
PIC18F45J10
OSC2 (HS Mode)
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3.4 PLL Frequency Multiplier
FIGURE 3-4: PLL BLOCK DIAGRAM
A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. For these reasons, the HSPLL and ECPLL modes are available. The HSPLL and ECPLL modes provide the ability to selectively run the device at 4 times the external oscillating source to produce frequencies up to 40 MHz. The PLL is enabled by setting the PLLEN bit in the OSCTUNE register (Register 3-1).
/4 HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE)
OSC2
HS or EC OSC1 Mode
FIN FOUT
Phase Comparator
Loop Filter
VCO MUX
SYSCLK
REGISTER 3-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
OSCTUNE: PLL CONTROL REGISTER
R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
PLLEN(1)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PLLEN: Frequency Multiplier PLL Enable bit(1) 1 = PLL enabled 0 = PLL disabled Unimplemented: Read as `0' Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads as `0'.
bit 5-0 Note 1:
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3.5 Internal Oscillator Block
The PIC18F45J10 family of devices includes an internal oscillator source (INTRC) which provides a nominal 31 kHz output. The INTRC is enabled on device power-up and clocks the device during its configuration cycle until it enters operating mode. INTRC is also enabled if it is selected as the device clock source or if any of the following are enabled: * Fail-Safe Clock Monitor * Watchdog Timer * Two-Speed Start-up These features are discussed in greater detail in Section 21.0 "Special Features of the CPU". The INTRC can also be optionally configured as the default clock source on device start-up by setting the FOSC2 Configuration bit. This is discussed in Section 3.6.1 "Oscillator Control Register". The primary oscillators include the External Crystal and Resonator modes and the External Clock modes. The particular mode is defined by the FOSC<2:0> Configuration bits. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F45J10 family devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC). Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.3 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F45J10 family devices are shown in Figure 3-5. See Section 21.0 "Special Features of the CPU" for Configuration register details.
3.6
Clock Sources and Oscillator Switching
The PIC18F45J10 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate clock source. PIC18F45J10 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator
FIGURE 3-5:
PIC18F45J10 FAMILY CLOCK DIAGRAM
PIC18F45J10 Family Primary Oscillator Sleep HS, EC 4 x PLL HSPLL, ECPLL MUX T1OSC Peripherals
OSC2
OSC1 T1OSO T1OSI Secondary Oscillator T1OSCEN Enable Oscillator
INTRC Source
Internal Oscillator CPU IDLEN
Clock Control FOSC<2:0>
OSCCON<1:0>
Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up
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3.6.1 OSCILLATOR CONTROL REGISTER 3.6.1.1
The OSCCON register (Register 3-2) controls several aspects of the device clock's operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator. The clock source changes after one or more of the bits are written to, following a brief clock transition interval. The OSTS (OSCCON<3>) and T1RUN (T1CON<6>) bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The T1RUN bit indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If neither of these bits is set, the INTRC is providing the clock, or the internal oscillator has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts.
System Clock Selection and the FOSC2 Configuration Bit
The SCS bits are cleared on all forms of Reset. In the device's default configuration, this means the primary oscillator defined by FOSC<1:0> (that is, one of the HC or EC modes) is used as the primary clock source on device Resets. The default clock configuration on Reset can be changed with the FOSC2 Configuration bit. The effect of this bit is to set the clock source selected when SCS<1:0> = 00. When FOSC2 = 1 (default), the oscillator source defined by FOSC<1:0> is selected whenever SCS<1:0> = 00. When FOSC2 = 0, the INTRC oscillator is selected whenever SCS<1:0> = 00. Because the SCS bits are cleared on Reset, the FOSC2 setting also changes the default oscillator mode on Reset. Regardless of the setting of FOSC2, INTRC will always be enabled on device power-up. It will serve as the clock source until the device has loaded its configuration values from memory. It is at this point that the FOSC Configuration bits are read and the oscillator selection of operational mode is made. Note that either the primary clock or the internal oscillator will have two bit setting options, at any given time, depending on the setting of FOSC2.
3.6.2
OSCILLATOR TRANSITIONS
PIC18F45J10 family devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 "Entering Power-Managed Modes".
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REGISTER 3-2:
R/W-0 IDLEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OSCCON: OSCILLATOR CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R-q(1) OSTS U-0 -- R/W-0 SCS1 R/W-0 SCS0 bit 0
IDLEN: Idle Enable bit 1 = Device enters an Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction Unimplemented: Read as `0' OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready Unimplemented: Read as `0' SCS<1:0>: System Clock Select bits(4) 11 = Internal oscillator 10 = Primary oscillator 01 = Timer1 oscillator When FOSC2 = 1: 00 = Primary oscillator When FOSC2 = 0: 00 = Internal oscillator The Reset value is `0' when HS mode and Two-Speed Start-up are both enabled; otherwise, it is `1'.
bit 6-4 bit 3
bit 2 bit 1-0
Note 1:
3.7
Effects of Power-Managed Modes on the Various Clock Sources
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In RC_RUN and RC_IDLE modes, the internal oscillator provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 21.2 "Watchdog Timer (WDT)" through Section 21.5 "Fail-Safe Clock Monitor" for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a real-time clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 24.2 "DC Characteristics: Power-Down and Supply Current".
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3.8 Power-up Delays
Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.6 "Power-up Timer (PWRT)". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 24-10). It is always enabled. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval, TCSD (parameter 38, Table 24-10), following POR, while the controller becomes ready to execute instructions.
TABLE 3-3:
EC, ECPLL HS, HSPLL Note:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level OSC2 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level
Oscillator Mode
See Table 5-2 in Section 5.0 "Reset" for time-outs due to Sleep and MCLR Reset.
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NOTES:
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4.0 POWER-MANAGED MODES
4.1.1 CLOCK SOURCES
The PIC18F45J10 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: * Run mode * Idle mode * Sleep mode These modes define which portions of the device are clocked and at what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several power-saving features offered on previous PIC(R) microcontrollers. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC microcontrollers, where all device clocks are stopped. The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: * the primary clock, as defined by the FOSC<1:0> Configuration bits * the secondary clock (Timer1 oscillator) * the internal oscillator
4.1.2
ENTERING POWER-MANAGED MODES
Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 4.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and which clock source is to be used. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1.
TABLE 4-1:
Mode Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1:
POWER-MANAGED MODES
OSCCON bits IDLEN<7>(1) 0 N/A N/A N/A 1 1 1 SCS<1:0> N/A 10 01 11 10 01 11 Module Clocking Available Clock and Oscillator Source CPU Off Clocked Clocked Clocked Off Off Off Peripherals Off Clocked Clocked Clocked Clocked Clocked Clocked None - All clocks are disabled Primary - HS, EC; this is the normal full-power execution mode Secondary - Timer1 Oscillator Internal Oscillator Primary - HS, EC Secondary - Timer1 Oscillator Internal Oscillator
IDLEN reflects its value when the SLEEP instruction is executed.
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4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS 4.2.2 SEC_RUN MODE
The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. Note: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit. The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
4.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting.
4.2
Run Modes
In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source.
On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 21.4 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set. (see Section 3.6.1 "Oscillator Control Register").
FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 Clock Transition n-1 n Q3 Q4 Q1 Q2 Q3
T1OSI OSC1 CPU Clock Peripheral Clock Program Counter PC
PC + 2
PC + 4
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4.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. This mode is entered by setting SCS<1:0> to `11'. When the clock source is switched to the INTRC (see Figure 4-2), the primary oscillator is shut down and the OSTS bit is cleared. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-3). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 4-2:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 Clock Transition n-1 n Q3 Q4 Q1 Q2 Q3
INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC
PC + 2
PC + 4
FIGURE 4-3:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1 INTRC OSC1 TOST(1) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed PC OSTS bit Set PC + 2 PC + 4
Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.
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4.3 Sleep Mode 4.4 Idle Modes
The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC microcontrollers. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-4). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-5), or it will be clocked from the internal oscillator if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 21.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 24-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits.
FIGURE 4-4:
OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
PC + 2
FIGURE 4-5:
TRANSITION TIMING FOR WAKE FROM SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 TOST(1) CPU Clock Peripheral Clock Program Counter Wake Event PC OSTS bit Set PC + 2 PC + 4 PC + 6
Note1: TOST = 1024 TOSC. These intervals are not shown to scale.
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4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE
This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set the SCS<1:0> bits to `10' and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC0 Configuration bit. The OSTS bit remains set (see Figure 4-6). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-7). In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS<1:0> to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut-down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 4-7). Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
FIGURE 4-6:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2
FIGURE 4-7:
Q1 OSC1 CPU Clock Peripheral Clock Program Counter
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q2 Q3 Q4
TCSD
PC
Wake Event
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4.4.3 RC_IDLE MODE 4.5.2 EXIT BY WDT TIME-OUT
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP. When the clock source is switched to the INTRC, the primary oscillator is shut down and the OSTS bit is cleared. When a wake event occurs, the peripherals continue to be clocked from the INTRC. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTRC. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 "Run Modes" and Section 4.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 21.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by one of the following events: * executing a SLEEP or CLRWDT instruction * the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled)
4.5.3
EXIT BY RESET
4.5
Exiting Idle and Sleep Modes
Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC.
An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes sections (see Section 4.2 "Run Modes", Section 4.3 "Sleep Mode" and Section 4.4 "Idle Modes").
4.5.4
EXIT WITHOUT AN OSCILLATOR START-UP DELAY
Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode where the primary clock source is not stopped; and * the primary clock source is the EC mode. In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC). However, a fixed delay of interval, TCSD, following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the device to exit from an Idle mode, or the Sleep mode, to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 "Interrupts"). A fixed delay of interval, TCSD, following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
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5.0 RESET
5.1 RCON Register
The PIC18F45J10 family of devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) i) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Configuration Mismatch (CM) Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Device Reset events are tracked through the RCON register (Register 5-1). The lower six bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be set by the event and must be cleared by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.7 "Reset State of Registers". The RCON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed in Section 9.0 "Interrupts".
This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 6.1.4.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 21.2 "Watchdog Timer (WDT)". A simplified block diagram of the on-chip Reset circuit is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Configuration Word Mismatch Stack Pointer Stack Full/Underflow Reset
External Reset MCLR
( )_IDLE Sleep WDT Time-out VDD Rise Detect POR Pulse
VDD
Brown-out Reset(1) S PWRT 32 s INTRC PWRT 66 ms R Q Chip_Reset
11-Bit Ripple Counter
Note 1:
The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
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REGISTER 5-1:
R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCON: RESET CONTROL REGISTER
U-0 -- R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR(1) bit 0
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit(1) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) BOR is not available on PIC18LF2XJ10/4XJ10 devices.
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains `0' at all times. See Section 5.4.1 "Detecting BOR" for more information. 3: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset).
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5.2 Master Clear (MCLR)
FIGURE 5-2:
The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
VDD D
R R1 C MCLR
5.3
Power-on Reset (POR)
Note 1:
PIC18F45J10
A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. Power-on Reset events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any Power-on Reset.
External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
2:
3:
5.4.1
DETECTING BOR
The BOR bit always resets to `0' on any Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any Power-on Reset event. If BOR is `0' while POR is `1', it can be reliably assumed that a Brown-out Reset event has occurred. In devices designated with an "LF" part number (such as PIC18LF25J10), Brown-out Reset functionality is disabled. In this case, the BOR bit cannot be used to determine a Brown-out Reset event. The BOR bit is still cleared by a Power-on Reset event.
5.4
Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)
The PIC18F45J10 family of devices incorporates a simple BOR function when the internal regulator is enabled (ENVREG pin is tied to VDD). Any drop of VDD below VBOR (parameter D005) for greater than time TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. Once a BOR has occurred, the Power-up Timer will keep the chip in Reset for TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay.
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5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT)
The Configuration Mismatch (CM) Reset is designed to detect and attempt to recover from random, memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread, single-bit changes throughout the device and result in catastrophic failure. In PIC18FXXJ Flash devices, the device Configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>). The state of the bit is set to `0' whenever a CM event occurs; it does not change for any other Reset event. A CM Reset behaves similarly to a Master Clear Reset, RESET instruction, WDT time-out or Stack Event Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. PIC18F45J10 family devices incorporate an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F45J10 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation. See DC parameter 33 for details.
5.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR pulse has cleared. The total time-out will vary based on the status of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5 and Figure 5-6 all depict time-out sequences on power-up with the Power-up Timer enabled. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes, or to synchronize more than one PIC18F device operating in parallel.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
INTERNAL RESET
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FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V VDD MCLR 0V 1V
INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET
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5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 5-1. These bits are used in software to determine the nature of the Reset. Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER
Program Counter(1) 0000h 0000h 0000h 0000h 0000h 0000h RCON Register CM 1 u 1 0 u u RI 1 0 1 u u u TO 1 u 1 u 1 1 PD 1 u 1 u u 0 POR 0 u u u u u STKPTR Register BOR(2) STKFUL 0 u 0 u u u 0 u u u u u STKUNF 0 u u u u u
Condition Power-on Reset RESET instruction Brown-out Reset Configuration Mismatch Reset MCLR Reset during power-managed Run modes MCLR Reset during power-managed Idle modes and Sleep mode MCLR Reset during full-power execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT time-out during full-power or power-managed Run modes WDT time-out during power-managed Idle or Sleep modes Interrupt exit from power-managed modes
0000h 0000h 0000h 0000h 0000h PC + 2
u u u u u u
u u u u u u
u u u u 0 0
u u u u u 0
u u u u u u
u u u u u u
u 1 u u u u
u u 1 1 u u
PC + 2
u
u
u
0
u
u
u
u
Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 2: BOR is not available on PIC18LF2XJ10/4XJ10 devices.
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TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- 0000 Wake-up via WDT or Interrupt
Register
Applicable Devices
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR
PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10
---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx ---- 0000
---0 uuuu(1) uuuu uuuu(1) uuuu uuuu(1) uu-u uuuu(1) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(3) uuuu -u-u(3) uu-u u-uu(3) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition.
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TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0--- q-00 ---- ---0 0-qq qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0-00 0000 --00 0qqq 0-00 0000 Wake-up via WDT or Interrupt
Register
Applicable Devices
INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON WDTCON RCON
(4)
PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10
N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0--- q-00 ---- ---0 0-11 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0-00 0000 --00 0qqq 0-00 0000
N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- q-uu ---- ---u u-uu qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu --uu uqqq u-uu uuuu
TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition.
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TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0111 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0010 0000 000x 0000 0000 ---0 x0011-- ---00-- ---00-- ---11-- 1--1 00-- 0--0 00-- 0--0 1111 1111 0000 0000 0000 0000 Wake-up via WDT or Interrupt
Register
Applicable Devices
CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON BAUDCON ECCP1DEL ECCP1AS CVRCON CMCON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1
PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10
xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0111 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0010 0000 000x 0000 0000 ---0 x0011-- ---00-- ---00-- ---11-- 1--1 00-- 0--0 00-- 0--0 1111 1111 0000 0000 0000 0000
uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uu-u u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuuu-- ---uu-- ----(3) uu-- ---uu-- u--u uu-- u--u(3) uu-- u--u uuuu uuuu uuuu uuuu(3) uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition.
(c) 2009 Microchip Technology Inc.
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TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets 1111 -111 1111 1111 1111 1111 1111 1111 --1- 1111 uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --0- 0000 Wake-up via WDT or Interrupt
Register
Applicable Devices
TRISE TRISD TRISC TRISB TRISA SSP2BUF LATE LATD LATC LATB LATA SSP2ADD SSP2STAT SSP2CON1 SSP2CON2 PORTE PORTD PORTC PORTB PORTA
PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10 PIC18F2XJ10 PIC18F4XJ10
0000 -111 1111 1111 1111 1111 1111 1111 --1- 1111 xxxx xxxx ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx --xx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx --0- 0000
uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition.
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6.0 MEMORY ORGANIZATION
6.1 Program Memory Organization
There are two types of memory in PIC18 Enhanced microcontroller devices: * Program Memory * Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 "Flash Program Memory". PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The PIC18F24J10 and PIC18F44J10 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F25J10 and PIC18F45J10 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for the PIC18F45J10 family devices is shown in Figure 6-1.
FIGURE 6-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F45J10 FAMILY DEVICES
PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1
* * *
21
Stack Level 31 Reset Vector High-Priority Interrupt Vector Low-Priority Interrupt Vector On-Chip Program Memory On-Chip Program Memory 0000h 0008h 0018h
PIC18FX4J10 7FF7h 8000h PIC18FX5J10
Read `0'
Read `0'
1FFFFFh 200000h
(c) 2009 Microchip Technology Inc.
User Memory Space
3FF7h 4000h
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6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. PIC18 devices also have two interrupt vector addresses for the handling of high-priority and lowpriority interrupts. The high-priority interrupt vector is located at 0008h and the low-priority interrupt vector is at 0018h. Their locations in relation to the program memory map are shown in Figure 6-2. Because PIC18F45J10 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. On Reset, the configuration information is copied into the Configuration registers. The Configuration Words are stored in their program memory location in numerical order, starting with the lower byte of CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. For these devices, only Configuration Words, CONFIG1 through CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F45J10 family are shown in Table 6-1. Their location in the memory map is shown with the other memory vectors in Figure 6-2. Additional details on the device Configuration Words are provided in Section 21.1 "Configuration Bits".
FIGURE 6-2:
HARD VECTOR AND CONFIGURATION WORD LOCATIONS FOR PIC18F45J10 FAMILY DEVICES
0000h 0008h 0018h
Reset Vector High-Priority Interrupt Vector Low-Priority Interrupt Vector
TABLE 6-1:
FLASH CONFIGURATION WORD FOR PIC18F45J10 FAMILY DEVICES
Program Memory (Kbytes) 16 32 Configuration Word Addresses 3FF8h to 3FFFh 7FF8h to 7FFFh
Device PIC18F24J10 PIC18F44J10 PIC18F25J10 PIC18F45J10
On-Chip Program Memory
Flash Configuration Words
(Top of Memory-7) (Top of Memory)
Read `0'
1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale.
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6.1.3 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 6.1.6.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the top-ofstack Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed.
6.1.4.1
Top-of-Stack Access
6.1.4
RETURN ADDRESS STACK
The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 6-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.
FIGURE 6-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack<20:0> 11111 11110 11101
Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 001A34h 000D58h
Stack Pointer STKPTR<4:0> 00010
00011 00010 00001 00000
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6.1.4.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Overflow) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 21.1 "Configuration Bits" for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.
6.1.4.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.
REGISTER 6-1:
R/C-0 STKFUL(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STKPTR: STACK POINTER REGISTER
R/C-0 U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
STKUNF(1)
STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP<4:0>: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software or by a POR.
bit 6
bit 5 bit 4-0 Note 1:
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6.1.4.4 Stack Full and Underflow Resets 6.1.6
Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset.
LOOK-UP TABLES IN PROGRAM MEMORY
There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads
6.1.6.1
Computed GOTO
6.1.5
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS, WREG and BSR registers, to provide a "fast return" option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high-priority interrupts are enabled, the stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. Example 6-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return.
A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.
EXAMPLE 6-2:
MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . .
COMPUTED GOTO USING AN OFFSET VALUE
OFFSET, W TABLE PCL nnh nnh nnh
ORG TABLE
6.1.6.2
Table Reads and Table Writes
EXAMPLE 6-1:
CALL SUB1, FAST
FAST REGISTER STACK CODE EXAMPLE
;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK
A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 "Table Reads and Table Writes".
* * SUB1 * * RETURN, FAST
;RESTORE VALUES SAVED ;IN FAST REGISTER STACK
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6.2
6.2.1
PIC18 Instruction Cycle
CLOCKING SCHEME
6.2.2
INSTRUCTION FLOW/PIPELINING
The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 6-4.
An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 6-4:
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode)
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Internal Phase Clock
PC PC + 2 PC + 4
Execute INST (PC - 2) Fetch INST (PC)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 2) Fetch INST (PC + 4)
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
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6.2.3 INSTRUCTIONS IN PROGRAM MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 6.1.3 "Program Counter"). Figure 6-5 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 6-5 shows how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 22.0 "Instruction Set Summary" provides further details of the instruction set.
FIGURE 6-5:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 Program Memory Byte Locations LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h
Instruction 1: Instruction 2: Instruction 3:
MOVLW GOTO MOVFF
055h 0006h 123h, 456h
0Fh EFh F0h C1h F4h
55h 03h 00h 23h 56h
6.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence - immediately after the first word - the data in the second word is accessed and used by
the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 shows how this works. Note: See Section 6.6 "PIC18 Instruction Execution and the Extended Instruction Set" for information on two-word instructions in the extended instruction set.
EXAMPLE 6-4:
CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000
TWO-WORD INSTRUCTIONS
Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code
0000 0011 0110 0000
0000 0011 0110 0000
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6.3
Note:
Data Memory Organization
The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.5 "Data Memory and the Extended Instruction Set" for more information.
6.3.1
BANK SELECT REGISTER (BSR)
The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F45J10 family devices implement all 16 banks. Figure 6-6 shows the data memory organization for the PIC18F45J10 family devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 "Access Bank" provides a detailed description of the Access RAM.
Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location's address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 6-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.
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FIGURE 6-6:
BSR<3:0> = 0000 00h Bank 0 FFh 00h Bank 1 Bank 2 FFh 00h GPR FFh 00h GPR FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h 3FFh 400h 4FFh 500h 5FFh 600h 6FFh 700h 7FFh 800h 8FFh 900h 9FFh A00h AFFh B00h BFFh C00h CFFh D00h DFFh E00h EFFh F00h F7Fh F80h FFFh Access Bank 7Fh Access RAM High 80h (SFRs) FFh Access RAM Low 00h 2FFh 300h When `a' = 1: The BSR specifies the Bank used by the instruction.
DATA MEMORY MAP FOR PIC18F45J10 FAMILY DEVICES
Data Memory Map Access RAM GPR GPR 1FFh 200h 000h 07Fh 080h 0FFh 100h When `a' = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15).
= 0001 = 0010
= 0011
Bank 3
= 0100 = 0101
Bank 4
Bank 5
= 0110
Bank 6
= 0111
Bank 7
= 1000
Bank 8
= 1001
Bank 9
Unused Read 00h
= 1010
Bank 10
= 1011
Bank 11
= 1100
Bank 12
= 1101
FFh Bank 13 00h FFh 00h FFh 00h Bank 15 FFh
= 1110
Bank 14
= 1111
Unused
SFR
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FIGURE 6-7:
7
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1) 0 000h 100h 200h 300h Bank 2
Data Memory
00h Bank 0 Bank 1 FFh 00h FFh 00h FFh 00h 7
From Opcode(2)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Bank Select(2)
Bank 3 through Bank 13
E00h Bank 14 F00h FFFh Note 1: 2: Bank 15
FFh 00h FFh 00h FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction.
6.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. This upper half is also where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 6-6). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0',
however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 6.5.3 "Mapping the Access Bank in Indexed Literal Offset Mode".
6.3.3
GENERAL PURPOSE REGISTER FILE
PIC18 devices may have banked memory in the GPR area. This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets.
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6.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 6-2 and Table 6-3. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's.
TABLE 6-2:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh
SPECIAL FUNCTION REGISTER MAP FOR PIC18F45J10 FAMILY DEVICES
Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1) Address FDFh Name INDF2
(1) (1)
Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h
Name CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON --(2) BAUDCON ECCP1DEL(3) ECCP1AS(3) CVRCON CMCON --(2) --(2) --(2) SPBRGH SPBRG RCREG TXREG TXSTA RCSTA --(2) --(2) --(2) EECON2(1) EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2
Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h
Name IPR1 PIR1 PIE1 --(2) --(2) --(2) --(2) --(2) --(2) TRISE(3) TRISD(3) TRISC TRISB TRISA --(2) --(2) --(2) SSP2BUF LATE(3) LATD(3) LATC LATB LATA SSP2ADD(3)
FDEh POSTINC2 FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h
FDDh POSTDEC2(1) PREINC2(1) PLUSW2(1) FSR2H FSR2L STATUS TMR0H TMR0L T0CON --(2) OSCCON --(2) WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2
FEEh POSTINC0(1) FEDh POSTDEC0(1) FECh FEBh FEAh FE9h FE8h FE7h FE5h FE4h FE3h FE2h FE1h FE0h Note 1: 2: 3: PREINC0(1) PLUSW0 FSR0L WREG INDF1(1) POSTDEC1(1) PREINC1(1) PLUSW1 FSR1L BSR
(1) (1)
FSR0H
F87h SSP2STAT(3) F86h SSP2CON1(3) F85h SSP2CON2(3) F84h F83h F82h F81h F80h PORTE(3) PORTD(3) PORTC PORTB PORTA
FE6h POSTINC1(1)
FSR1H
This is not a physical register. Unimplemented registers are read as `0'. This register is not available in 28-pin devices.
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TABLE 6-3:
File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS Legend: Note 1: 2: 3:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10)
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 ---0 0000 0000 0000 0000 0000 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 -- INT0IE INTEDG2 INT2IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx Bank Select Register ---- 0000 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx OV Z DC C ---x xxxx Details on page: 47, 53 47, 53 47, 53 47, 54 47, 53 47, 53 47, 53 47, 74 47, 74 47, 74 47, 74 47, 81 47, 81 47, 85 47, 86 47, 87 47, 67 47, 67 47, 67 47, 67 47, 67 47, 67 47, 67 47 47, 67 47, 67 47, 67 47, 67 47, 67 47, 67 47, 67 47, 58 48, 67 48, 67 48, 67 48, 67 48, 67 48, 67 48, 67 48, 65
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- --
Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W -- Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 1 High Byte Indirect Data Memory Address Pointer 1 Low Byte Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W -- -- -- -- -- -- -- N Indirect Data Memory Address Pointer 2 High Byte Indirect Data Memory Address Pointer 2 Low Byte -- -- -- Indirect Data Memory Address Pointer 0 High Byte Indirect Data Memory Address Pointer 0 Low Byte
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition See Section 5.4 "Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)". These registers and/or bits are not implemented on 28-pin devices and are read as `0'. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as `-'. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 16.4.3.2 "Address Masking" for details.
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TABLE 6-3:
File Name TMR0H TMR0L T0CON OSCCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON BAUDCON ECCP1DEL ECCP1AS CVRCON CMCON Legend: Note 1: 2: 3:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 xxxx xxxx T0CS -- -- CM T0SE -- -- RI PSA OSTS -- TO T0PS2 -- -- PD T0PS1 SCS1 -- POR T0PS0 SCS0 SWDTEN BOR(1) 1111 1111 0--- q-00 --- ---0 Details on page: 48, 117 48, 117 48, 115 32, 48 48, 242 48, 124 48, 124 48, 119 48, 126 48, 126 48, 125 48, 158 48, 159 48, 150, 160 48, 151, 161 48, 162 48, 163 48, 223 48, 223 48, 218 48, 218 48, 218 49, 128 49, 128 49, 128, 49, 128 49, 128 49, 128 49, 196 49, 144 49, 146 49, 232 49, 226
Timer0 Register High Byte Timer0 Register Low Byte TMR0ON IDLEN -- IPEN T08BIT -- -- --
0-11 11q0 42, 46, 94 xxxx xxxx xxxx xxxx
Timer1 Register High Byte Timer1 Register Low Byte RD16 Timer2 Register Timer2 Period Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 MSSP1 Receive Buffer/Transmit Register MSSP1 Address Register in I2CTM Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode. SMP WCOL GCEN GCEN CKE SSPOV ACKSTAT ACKSTAT D/A SSPEN ACKDT ADMSK5(3) P CKP ACKEN ADMSK4(3) S SSPM3 RCEN ADMSK3(3) R/W SSPM2 PEN ADMSK2(3) UA SSPM1 RSEN ADMSK1(3) BF SSPM0 SEN SEN T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
A/D Result Register High Byte A/D Result Register Low Byte ADCAL -- ADFM -- -- -- CHS3 VCFG1 ACQT2 CHS2 VCFG0 ACQT1 CHS1 PCFG3 ACQT0 CHS0 PCFG2 ADCS2 GO/DONE PCFG1 ADCS1 ADON PCFG0 ADCS0
0-00 0000 --00 0qqq 0-00 0000 xxxx xxxx xxxx xxxx
Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte -- ABDOVF PRSEN ECCPASE CVREN C2OUT -- RCIDL PDC6(2) ECCPAS2 CVROE C1OUT DC2B1 -- PDC5(2) ECCPAS1 CVRR C2INV DC2B0 SCKP PDC4(2) ECCPAS0 CVRSS C1INV CCP2M3 BRG16 PDC3(2) PSSAC1 CVR3 CIS CCP2M2 -- PDC2(2) PSSAC0 CVR2 CM2 CCP2M1 WUE PDC1(2) PSSBD1(2) CVR1 CM1 CCP2M0 ABDEN PDC0(2) CVR0 CM0
0000 0000 xxxx xxxx xxxx xxxx --00 0000 01-0 0-00 0000 0000
PSSBD0(2) 0000 0000 0000 0000 0000 0111
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition See Section 5.4 "Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)". These registers and/or bits are not implemented on 28-pin devices and are read as `0'. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as `-'. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 16.4.3.2 "Address Masking" for details.
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TABLE 6-3:
File Name SPBRGH SPBRG RCREG TXREG TXSTA RCSTA EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 TRISE(2) TRISD(2) TRISC TRISB TRISA SSP2BUF LATE(2) LATD(2) LATC LATB LATA SSP2ADD SSP2STAT SSP2CON1 SSP2CON2 PORTE(2) PORTD(2) PORTC PORTB PORTA Legend: Note 1: 2: 3:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 0000 0000 0000 0000 xxxx xxxx TXEN SREN -- -- -- -- -- -- -- RCIP RCIF RCIE IBOV SYNC CREN FREE -- -- -- -- -- -- TXIP TXIF TXIE PSPMODE SENDB ADDEN WRERR -- -- -- BCL1IP BCL1IF BCL1IE SSP1IP SSP1IF SSP1IE -- BRGH FERR WREN -- -- -- -- -- -- CCP1IP CCP1IF CCP1IE TRISE2 TRMT OERR WR -- -- -- -- -- -- TMR2IP TMR2IF TMR2IE TRISE1 TX9D RX9D -- -- -- -- CCP2IP CCP2IF CCP2IE TMR1IP TMR1IF TMR1IE TRISE0 0000 0010 0000 000x 0000 0000 ---0 x0011-- ---00-- ---00-- ---11-- 1--1 00-- 0--0 00-- 0--0 1111 1111 0000 0000 0000 0000 0000 -111 1111 1111 1111 1111 1111 1111 -- -- TRISA3 -- TRISA2 TRISA1 TRISA0 --1- 1111 xxxx xxxx PORTE Data Latch Register (Read and Write to Data Latch) ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx --xx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx --0- 0000 Details on page: 49, 198 49, 198 49, 205 49, 203 49, 196 49, 195 49, 72 49, 74 49, 94 49, 90 49, 92 49, 93 49, 89 49, 91 49, 92 49, 88 49, 91 50, 112 50, 107 50, 104 50, 101 50, 98 50, 158 50, 110 50, 107 50, 104 50, 101 50, 98 50, 158 50, 150, 160 50, 151, 161 50, 164 48, 163 50, 110 50, 107 50, 104 50, 101 50, 98
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte EUSART Receive Register EUSART Transmit Register CSRC SPEN -- SSP2IP SSP2IF SSP2IE OSCFIP OSCFIF OSCFIE PSPIP(2) PSPIF(2) PSPIE(2) IBF TX9 RX9 -- BCL2IP BCL2IF BCL2IE CMIP CMIF CMIE ADIP ADIF ADIE OBF
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Control Register PORTC Data Direction Control Register PORTB Data Direction Control Register -- -- -- -- TRISA5 -- MSSP2 Receive Buffer/Transmit Register
PORTD Data Latch Register (Read and Write to Data Latch) PORTC Data Latch Register (Read and Write to Data Latch) PORTB Data Latch Register (Read and Write to Data Latch) -- SMP WCOL GCEN GCEN -- RD7 RC7 RB7 -- -- CKE SSPOV ACKSTAT ACKSTAT -- RD6 RC6 RB6 -- PORTA Data Latch Register (Read and Write to Data Latch) D/A SSPEN ACKDT ADMSK5(3) -- RD5 RC5 RB5 RA5 P CKP ACKEN ADMSK4(3) -- RD4 RC4 RB4 -- S SSPM3 RCEN ADMSK3(3) -- RD3 RC3 RB3 RA3 R/W SSPM2 PEN ADMSK2(3) RE2(2) RD2 RC2 RB2 RA2 UA SSPM1 RSEN ADMSK1(3) RE1(2) RD1 RC1 RB1 RA1 BF SSPM0 SEN SEN RE0(2) RD0 RC0 RB0 RA0 MSSP2 Address Register in I2CTM Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode.
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition See Section 5.4 "Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)". These registers and/or bits are not implemented on 28-pin devices and are read as `0'. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as `-'. Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. See Section 16.4.3.2 "Address Masking" for details.
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6.3.5 STATUS REGISTER
The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 22-2 and Table 22-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction.
REGISTER 6-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
STATUS REGISTER
U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC
(1)
R/W-x C(2) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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6.4
Note:
Data Addressing Modes
The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.5 "Data Memory and the Extended Instruction Set" for more information.
The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 6.3.1 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register.
While the program memory can be addressed in only one way - through the program counter - information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect
6.4.3
INDIRECT ADDRESSING
An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 6.5.1 "Indexed Addressing with Literal Offset".
6.4.1
INHERENT AND LITERAL ADDRESSING
Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address.
Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 6-5.
EXAMPLE 6-5:
HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING
FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue
6.4.2
DIRECT ADDRESSING
NEXT
LFSR CLRF
Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 "General Purpose Register File") or a location in the Access Bank (Section 6.3.2 "Access Bank") as the data source for the instruction.
BTFSS BRA CONTINUE
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6.4.3.1 FSR Registers and the INDF Operand 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW
At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards * POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards * PREINC: increments the FSR value by 1, then uses it in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register, from FFh to 00h, carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.).
FIGURE 6-8:
INDIRECT ADDRESSING
000h ADDWF, INDF1, 1 100h Bank 1 200h Bank 2 Bank 0
Using an instruction with one of the Indirect Addressing registers as the operand....
...uses the 12-bit address stored in the FSR pair associated with that register....
FSR1H:FSR1L 7 0 7 0
300h
xxxx1110
11001100
Bank 3 through Bank 13
...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. E00h Bank 14 F00h FFFh Bank 15
Data Memory
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The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory.
6.5.1
INDEXED ADDRESSING WITH LITERAL OFFSET
6.4.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device.
Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0) and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in direct addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation.
6.5.2
INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is `1'), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 22.2.1 "Extended Instruction Syntax".
6.5
Data Memory and the Extended Instruction Set
Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remains unchanged.
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FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
Example Instruction: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When `a' = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
000h 060h 080h 100h Bank 1 through Bank 14 00h 60h 80h
Bank 0
Valid Range for `f'
F00h Bank 15 F80h SFRs FFFh Data Memory
Access RAM
FFh
When `a' = 0 and f 5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'.
000h Bank 0 080h 100h Bank 1 through Bank 14 FSR2H F00h Bank 15 F80h SFRs FFFh Data Memory FSR2L 001001da ffffffff
When `a' = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space.
000h Bank 0 080h 100h Bank 1 through Bank 14
BSR 00000000
001001da ffffffff
F00h Bank 15 F80h SFRs FFFh Data Memory
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6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 6.3.2 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 6-10. Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before.
6.6
PIC18 Instruction Execution and the Extended Instruction Set
Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 22.2 "Extended Instruction Set".
FIGURE 6-10:
Example Situation:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING
000h 05Fh 07Fh 100h 120h 17Fh 200h Bank 0 Bank 0 Bank 1 Window Bank 1 Bank 1 "Window" 5Fh Bank 0 Bank 2 through Bank 14 7Fh 80h
ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Locations in Bank 0 from 060h to 07Fh are mapped, as usual, to the middle half of the Access Bank. Special Function Registers at F80h through FFFh are mapped to 80h through FFh, as usual. Bank 0 addresses below 5Fh can still be addressed by using the BSR.
00h
SFRs FFh
Access Bank
F00h Bank 15 F80h FFFh SFRs
Data Memory
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7.0 FLASH PROGRAM MEMORY
7.1 Table Reads and Table Writes
The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 1024 bytes at a time. A Bulk Erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase; therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 7-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 7.5 "Writing to Flash Program Memory". Figure 7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL
Program Memory Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
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FIGURE 7-2: TABLE WRITE OPERATION
Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 "Writing to Flash Program Memory".
7.2
Control Registers
Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly.
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled.
The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation.
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REGISTER 7-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set S = Settable bit (cannot be cleared in software) `0' = Bit is cleared x = Bit is unknown
EECON1: EEPROM CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR U-0 -- bit 0
Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Performs an erase operation on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program 0 = Inhibits write cycles to Flash program WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete Unimplemented: Read as `0'
bit 3
bit 2
bit 1
bit 0
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7.2.2 TABLAT - TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 16 MSbs of the TBLPTR (TBLPTR<20:6>) determine which program memory block of 64 bytes is written to. For more detail, see Section 7.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 7 MSbs of the Table Pointer register (TBLPTR<20:10>) point to the 1024-byte block that will be erased. The Least Significant bits (TBLPTR<9:0>) are ignored. Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations.
7.2.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 7-1. These operations on the TBLPTR only affect the low-order 21 bits.
TABLE 7-1:
Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write
FIGURE 7-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
Table Erase TBLPTR<20:10> Table Write TBLPTR<20:6> Table Write TBLPTR<5:0>
Table Read - TBLPTR<21:0>
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7.3 Reading the Flash Program Memory
TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT.
The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time.
FIGURE 7-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register (IR)
FETCH
TBLRD
TABLAT Read Register
EXAMPLE 7-1:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word
TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVWF
TABLAT, W WORD_EVEN TABLAT, W WORD_ODD
; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data
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7.4 Erasing Flash Program Memory
7.4.1
The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 7 bits of the TBLPTR<21:10> point to the block being erased. TBLPTR<9:0> are ignored. The EECON1 register commands the erase operation. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory location is: 1. 2. 3. 4. 5. 6. 7. 8. Load Table Pointer register with address of the block being erased. Set the WREN and FREE bits (EECON1<2,4>) to enable the erase operation. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the erase cycle. The CPU will stall for duration of the erase for TIE (see parameter D133B). Re-enable interrupts.
EXAMPLE 7-2:
ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, WREN FREE GIE ; load TBLPTR with the base ; address of the memory block
ERASE_ROW BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts
Required Sequence
WR GIE
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7.5 Writing to Flash Program Memory
The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note: Unlike previous devices, the PIC18F45J10 family of devices does not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence. In order to maintain the endurance of the cells, each Flash byte should not be programmed more then twice between erase operations. Either a Bulk or Row Erase of the target row is required before attempting to modify the contents a third time.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT Write Register
8
TBLPTR = xxxxx0 TBLPTR = xxxxx1
8
TBLPTR = xxxxx2
8
TBLPTR = xxxx3F
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
7.5.1
FLASH PROGRAM MEMORY WRITE SEQUENCE
The sequence of events for programming an internal program memory location should be: 1. If the section of program memory to be written to has been programmed previously, then the memory will need to be erased before the write occurs (see Section 7.4.1 "Flash Program Memory Erase Sequence"). Write the 64 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set WREN to enable byte writes. Disable interrupts.
5. 6. 7. 8.
Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). 9. Re-enable interrupts. 10. Verify the memory (table read). An example of the required code is shown in Example 7-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register.
2. 3. 4.
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EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF RESTART_BUFFER MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF FILL_BUFFER ... WRITE_BUFFER MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVFF MOVWF TBLWT+* D'64' COUNTER POSTINC0, WREG TABLAT ; number of bytes in holding register ; read the new data from I2C, SPI, ; PSP, USART, etc. D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts ; Need to write 16 blocks of 64 to write ; one erase block of 1024 CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the memory block
; point to buffer
DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, WREN GIE
; ; ; ; ;
get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full
; enable write to memory ; disable interrupts ; write 55h ; ; ; ; write 0AAh start program (CPU stall) re-enable interrupts disable write to memory
Required Sequence
WR GIE WREN
DECFSZ WRITE_COUNTER BRA RESTART_BUFFER
; done with one write cycle ; if not done replacing the erase block
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7.5.2 WRITE VERIFY 7.5.4
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
PROTECTION AGAINST SPURIOUS WRITES
To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 21.0 "Special Features of the CPU" for more detail.
7.5.3
UNEXPECTED TERMINATION OF WRITE OPERATION
7.6
If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed.
Flash Program Operation During Code Protection
See Section 21.6 "Program Verification and Code Protection" for details on code protection of Flash program memory.
TABLE 7-2:
Name TBLPTRU
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7 -- Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 47 47 47 47 INT0IE FREE -- -- -- RBIE WRERR BCL1IP BCL1IF BCL1IE TMR0IF WREN -- -- -- INT0IF WR -- -- -- RBIF -- CCP2IP CCP2IF CCP2IE 47 49 49 49 49 49
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Program Memory Table Latch GIE/GIEH PEIE/GIEL TMR0IE -- OSCFIP OSCFIF OSCFIE -- CMIP CMIF CMIE -- -- -- -- EEPROM Control Register 2 (not a physical register)
Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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NOTES:
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8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
EXAMPLE 8-1:
MOVF MULWF ARG1, W ARG2
8 x 8 UNSIGNED MULTIPLY ROUTINE
; ; ARG1 * ARG2 -> ; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 8-1.
EXAMPLE 8-2:
MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F
8 x 8 SIGNED MULTIPLY ROUTINE
; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1
; Test Sign Bit ; PRODH = PRODH ; - ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.8 s 25.4 s 4.0 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s
8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed
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Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
EQUATION 8-2:
16 x 16 SIGNED MULTIPLICATION ALGORITHM
EQUATION 8-1:
16 x 16 UNSIGNED MULTIPLICATION ALGORITHM
ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L)
RES3:RES0
= =
RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216)
EXAMPLE 8-4:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE :
16 x 16 SIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L -> ; PRODH:PRODL ; ;
EXAMPLE 8-3:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
16 x 16 UNSIGNED MULTIPLY ROUTINE
; ARG1L * ARG2L-> ; PRODH:PRODL ; ;
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3
ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F
; ARG1H * ARG2H-> ; PRODH:PRODL ; ;
; ARG1H * ARG2H -> ; PRODH:PRODL ; ;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H-> PRODH:PRODL Add cross products
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
ARG1H * ARG2L -> PRODH:PRODL Add cross products
ARG1H * ARG2L-> PRODH:PRODL Add cross products
Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.
; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ;
ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3
; ARG1H:ARG1L neg? ; no, done ; ; ;
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9.0 INTERRUPTS
Members of the PIC18F45J10 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low-priority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) which re-enables interrupts. For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.
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FIGURE 9-1: PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC
TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Wake-up if in Idle or Sleep modes
PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> PIR3<7:6> PIE3<7:6> IPR3<7:6>
Interrupt to CPU Vector to Location 0008h
GIE/GIEH IPEN IPEN PEIE/GIEL IPEN
High-Priority Interrupt Generation Low-Priority Interrupt Generation
PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> PIR3<7:6> PIE3<7:6> IPR3<7:6>
TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP
IPEN
Interrupt to CPU Vector to Location 0018h
GIE/GIEH PEIE/GIEL
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9.1 INTCON Registers
Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
REGISTER 9-1:
R/W-0 GIE/GIEH bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(1) bit 0
PEIE/GIEL
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 9-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-1 INTEDG1 R/W-1 INTEDG2 U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP bit 0
INTEDG0
RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplemented: Read as `0' TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note:
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REGISTER 9-3:
R/W-1 INT2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1 INT1IP U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0
INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplemented: Read as `0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
Note:
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9.2 PIR Registers
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.
REGISTER 9-4:
R/W-0 PSPIF(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSP1IF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: ECCP1/CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow This bit is not implemented on 28-pin devices and should be read as `0'.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 9-5:
R/W-0 OSCFIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 CMIF U-0 -- U-0 -- R/W-0 BCLIF U-0 -- U-0 -- R/W-0 CCP2IF bit 0
OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as `0' BCLIF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred Unimplemented: Read as `0' CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode.
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
REGISTER 9-6:
R/W-0 SSP2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0 BCL2IF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred Unimplemented: Read as `0'
bit 6
bit 5-0
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9.3 PIE Registers
The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 9-7:
R/W-0 PSPIE(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSP1IE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt CCP1IE: ECCP1/CCP1 Interrupt Enable bit 1 = Enables the ECCP1/CCP1 interrupt 0 = Disables the ECCP1/CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt This bit is not implemented on 28-pin devices and should be read as `0'.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 9-8:
R/W-0 OSCFIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 CMIE U-0 -- U-0 -- R/W-0 BCL1IE U-0 -- U-0 -- R/W-0 CCP2IE bit 0
OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled Unimplemented: Read as `0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
REGISTER 9-9:
R/W-0 SSP2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0 BCL2IE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled Unimplemented: Read as `0'
bit 6
bit 5-0
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9.4 IPR Registers
The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
REGISTER 9-10:
R/W-1 PSPIP(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 RCIP R/W-1 TXIP R/W-1 SSP1IP R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 ADIP
R/W-1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority
bit 6
bit 5
bit 4
bit 3
SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit 1 = High priority 0 = Low priority CCP1IP: ECCP1/CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority This bit is not implemented on 28-pin devices and should be read as `0'.
bit 2
bit 1
bit 0
Note 1:
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REGISTER 9-11:
R/W-1 OSCFIP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0 -- U-0 -- R/W-1 BCL1IP U-0 -- U-0 -- R/W-0 CCP2IP bit 0
R/W-1 CMIP
OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority Unimplemented: Read as `0' CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
REGISTER 9-12:
R/W-1 SSP2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
R/W-1 BCL2IP
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority Unimplemented: Read as `0'
bit 6
bit 5-0
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9.5 RCON Register
The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
REGISTER 9-13:
R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
RCON: RESET CONTROL REGISTER
U-0 -- R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as `0' CM: Configuration Mismatch Flag bit For details of bit operation, see Register 5-1. RI: RESET Instruction Flag bit For details of bit operation, see Register 5-1. TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register 5-1. PD: Power-Down Detection Flag bit For details of bit operation, see Register 5-1. POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1.
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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9.6 INTx Pin Interrupts 9.7 TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from the power-managed modes if bit INTxIE was set prior to going into the power-managed modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 "Timer0 Module" for further details on the Timer0 module.
9.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section 6.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere
MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS
; Restore BSR ; Restore WREG ; Restore STATUS
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NOTES:
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10.0 I/O PORTS
10.1 I/O Port Pin Capabilities
Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Data Latch register) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1. When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than VDD input levels.
10.1.1
PIN OUTPUT DRIVE
The output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher loads, such as LEDs. All other ports are designed for small loads, typically indication only. Table 10-1 summarizes the output capabilities. Refer to Section 24.0 "Electrical Characteristics" for more details.
TABLE 10-1:
Port PORTA PORTD PORTE PORTB PORTC
OUTPUT DRIVE LEVELS
Drive Description
Minimum Intended for indication. Suitable for direct LED drive levels.
FIGURE 10-1:
GENERIC I/O PORT OPERATION
High
RD LAT Data Bus WR LAT or PORT
10.1.2
D CK Data Latch D Q Q I/O pin
INPUT PINS AND VOLTAGE CONSIDERATIONS
WR TRIS
CK TRIS Latch Input Buffer
The voltage tolerance of pins used as device inputs is dependent on the pin's input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V; a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should be avoided. Table 102 summarizes the input capabilities. Refer to Section 24.0 "Electrical Characteristics" for more details.
RD TRIS
TABLE 10-2:
Q D
INPUT VOLTAGE LEVELS
Tolerated Input Description
Port or Pin
EN EN RD PORT
PORTA<5:0> PORTB<5:0> PORTC<1:0> PORTE<2:0> PORTB<7:6> PORTC<7:2> PORTD<7:0> 5.5V Tolerates input levels above VDD, useful for most standard logic. VDD Only VDD input levels tolerated.
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10.1.3 INTERFACING TO A 5V SYSTEM
10.2
PORTA, TRISA and LATA Registers
Though the VDDMAX of the PIC18F45J10 family is 3.6V, these devices are still capable of interfacing with 5V systems, even if the VIH of the target system is above 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 10-2), clearing the LAT bit for that pin and manipulating the corresponding TRIS bit (Figure 10-1) to either allow the line to be pulled high or to drive the pin low. Only port pins that are tolerant of voltages up to 5.5V can be used for this type of interface (refer to Section 10.1.2 "Input Pins and Voltage Considerations").
PORTA is a 5-bit wide, bidirectional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins RA<3:0> and RA5 as A/D converter inputs is selected by clearing or setting the control bits in the ADCON1 register (A/D Control Register 1). Pins RA0 and RA3 may also be used as comparator inputs and RA5 may be used as the C2 comparator output by setting the appropriate bits in the CMCON register. To use RA<3:0> as digital inputs, it is also necessary to turn off the comparators. Note: On a Power-on Reset, RA5 and RA<3:0> are configured as analog inputs and read as `0'.
FIGURE 10-2:
+5V SYSTEM HARDWARE INTERFACE
+5V +5V Device
PIC18F45J10
RD7
EXAMPLE 10-1:
BCF LATD, 7 ; ; ; ; ;
COMMUNICATING WITH THE +5V SYSTEM
set up LAT register so changing TRIS bit will drive line low send a 0 to the 5V system send a 1 to the 5V system
All PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
BCF BCF
TRISD, 7 TRISD, 7
EXAMPLE 10-2:
CLRF PORTA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Configure comparators for digital input Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs
CLRF
LATA
MOVLW MOVWF MOVWF MOVWF MOVLW
07h ADCON1 07h CMCON 0CFh
MOVWF
TRISA
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TABLE 10-3:
Pin RA0/AN0
PORTA I/O SUMMARY
Function RA0 AN0 TRIS Setting 0 1 1 0 1 AN1 1 0 1 AN2 VREFCVREF 1 1 x 0 1 AN3 VREF+ 1 1 0 1 AN4 SS1 C2OUT 1 1 0 x x x x I/O O I I O I I O I I I O O I I I O I I I O O O I I I/O Type DIG TTL ANA DIG TTL ANA DIG TTL ANA ANA ANA DIG TTL ANA ANA DIG TTL ANA TTL DIG ANA DIG ANA ANA Description LATA<0> data output; not affected by analog input. PORTA<0> data input; disabled when analog input enabled. A/D Input Channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. LATA<1> data output; not affected by analog input. PORTA<1> data input; disabled when analog input enabled. A/D Input Channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. A/D and comparator voltage reference low input. Comparator voltage reference output. Enabling this feature disables digital I/O. LATA<3> data output; not affected by analog input. PORTA<3> data input; disabled when analog input enabled. A/D Input Channel 3 and Comparator C1+ input. Default input configuration on POR. A/D and comparator voltage reference high input. LATA<5> data output; not affected by analog input. PORTA<5> data input; disabled when analog input enabled. A/D Input Channel 4. Default configuration on POR. Slave select input for MSSP1 (MSSP1 module). Comparator 2 output; takes priority over port data. Main oscillator feedback output connection (HS mode). System cycle clock output (FOSC/4) in RC and EC Oscillator modes. Main oscillator input connection. Main clock input connection.
RA1/AN1
RA1
RA2/AN2/ VREF-/CVREF
RA2
RA3/AN3/VREF+
RA3
RA5/AN4/SS1/ C2OUT
RA5
OSC2/CLKO OSC1/CLKI Legend:
OSC2 CLKO OSC1 CLKI
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option).
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TABLE 10-4:
Name PORTA LATA TRISA ADCON1 CMCON CVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- -- -- C2OUT CVREN Bit 6 -- -- -- -- C1OUT CVROE Bit 5 RA5 TRISA5 VCFG1 C2INV CVRR Bit 4 -- -- VCFG0 C1INV CVRSS Bit 3 RA3 TRISA3 PCFG3 CIS CVR3 Bit 2 RA2 TRISA2 PCFG2 CM2 CVR2 Bit 1 RA1 TRISA1 PCFG1 CM1 CVR1 Bit 0 RA0 TRISA0 PCFG0 CM0 CVR0 Reset Values on page 50 50 50 48 49 49
PORTA Data Latch Register (Read and Write to Data Latch)
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA.
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10.3 PORTB, TRISB and LATB Registers
Four of the PORTB pins (RB<7:4>) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB<7:4>) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep mode or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). Clear flag bit, RBIF.
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB.
EXAMPLE 10-3:
CLRF PORTB ; ; ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Set RB<4:0> as digital I/O pins Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the Configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/KBI1/T0CKI/C1OUT pin.
CLRF
LATB
MOVLW MOVWF MOVLW
0Fh ADCON1 0CFh
MOVWF
TRISB
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB<4:0> are configured as analog inputs by default and read as `0'; RB<7:5> are configured as digital inputs.
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TABLE 10-5:
Pin RB0/INT0/FLT0/ AN12
PORTB I/O SUMMARY
Function RB0 TRIS Setting 0 1 INT0 FLT0 AN12 1 1 1 0 1 INT1 AN10 1 1 0 1 INT2 AN8 1 1 0 1 AN9 CCP2
(2)
I/O O I I I I O I I I O I I I O I I O I O I I I O I I I O O I I I O I I O I
I/O Type DIG TTL ST ST ANA DIG TTL ST ANA DIG TTL ST ANA DIG TTL ANA DIG ST DIG TTL TTL ANA DIG TTL TTL ST DIG DIG TTL TTL ST DIG TTL TTL DIG ST
Description LATB<0> data output; not affected by analog input. PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) External Interrupt 0 input. PWM Fault input (ECCP1/CCP1 module); enabled in software. A/D Input Channel 12.(1) LATB<1> data output; not affected by analog input. PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) External Interrupt 1 input. A/D Input Channel 10.(1) LATB<2> data output; not affected by analog input. PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) External Interrupt 2 input. A/D Input Channel 8.(1) LATB<3> data output; not affected by analog input. PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) A/D Input Channel 9.(1) CCP2 compare and PWM output. CCP2 capture input LATB<4> data output; not affected by analog input. PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) Interrupt-on-change pin. A/D Input Channel 11.(1) LATB<5> data output. PORTB<5> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-change pin. Timer0 clock input. Comparator 1 output; takes priority over port data. LATB<6> data output. PORTB<6> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-change pin. Serial execution (ICSPTM) clock input for ICSP and ICD operation.(3) LATB<7> data output. PORTB<7> data input; weak pull-up when RBPU bit is cleared. Interrupt-on-change pin. Serial execution data output for ICSP and ICD operation.(3) Serial execution data input for ICSP and ICD operation.(3)
RB1/INT1/AN10
RB1
RB2/INT2/AN8
RB2
RB3/AN9/CCP2
RB3
1 0 1
RB4/KBI0/AN11
RB4
0 1
KBI0 AN11 RB5/KBI1/T0CKI/ C1OUT RB5 KBI1 T0CKI C1OUT RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD Legend: Note 1: 2: 3:
1 1 0 1 1 1 0 0 1 1 x 0 1 1 x x
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Pins are configured as analog inputs by default. Alternate assignment for CCP2 when the CCP2MX Configuration bit is `0'. Default assignment is RC1. All other pin functions are disabled when ICSPTM or ICD are enabled.
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TABLE 10-6:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3 ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Reset Values on page 50 50 50 RBIE -- INT1IE PCFG3 TMR0IF TMR0IP -- PCFG2 INT0IF -- INT2IF PCFG1 RBIF RBIP INT1IF PCFG0 47 47 47 48
PORTB Data Latch Register (Read and Write to Data Latch) PORTB Data Direction Control Register GIE/GIEH PEIE/GIEL RBPU INT2IP -- INT1IP -- TMR0IE -- VCFG1 INT0IE INT2IE VCFG0 INTEDG0 INTEDG1 INTEDG2
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTB.
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10.4 PORTC, TRISC and LATC Registers
Note: On a Power-on Reset, these pins are configured as digital inputs. PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-7). The pins have Schmitt Trigger input buffers. RC1 is normally configured by Configuration bit, CCP2MX, as the default peripheral pin of the CCP2 module (default/erased state, CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information.
The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins.
EXAMPLE 10-4:
CLRF PORTC ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTC
Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
CLRF
LATC
MOVLW 0CFh
MOVWF TRISC
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TABLE 10-7:
Pin RC0/T1OSO/ T1CKI
PORTC I/O SUMMARY
Function RC0 T1OSO T1CKI TRIS Setting 0 1 x 1 0 1 T1OSI CCP2(1) x 0 1 0 1 CCP1 P1A(2) 0 1 0 I/O O I O I O I I O I O I O I O I/O Type DIG ST ANA ST DIG ST ANA DIG ST DIG ST DIG ST DIG LATC<0> data output. PORTC<0> data input. Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. Timer1 counter input. LATC<1> data output. PORTC<1> data input. Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2 compare and PWM output; takes priority over port data. CCP2 capture input. LATC<2> data output. PORTC<2> data input. ECCP1/CCP1 compare or PWM output; takes priority over port data. ECCP1/CCP1 capture input. ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. LATC<3> data output. PORTC<3> data input. SPI clock output (MSSP1 module); takes priority over port data. SPI clock input (MSSP1 module). I2CTM clock output (MSSP1 module); takes priority over port data. LATC<4> data output. PORTC<4> data input. SPI data input (MSSP1 module). I2C data output (MSSP1 module); takes priority over port data. LATC<5> data output. PORTC<5> data input. SPI data output (MSSP1 module); takes priority over port data. LATC<6> data output. PORTC<6> data input. Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. Synchronous serial clock output (EUSART module); takes priority over port data. Synchronous serial clock input (EUSART module). LATC<7> data output. PORTC<7> data input. Asynchronous serial receive data input (EUSART module). Synchronous serial data output (EUSART module); takes priority over port data. Synchronous serial data input (EUSART module). User must configure as an input. Description
RC1/T1OSI/CCP2
RC1
RC2/CCP1/P1A
RC2
RC3/SCK1/SCL1
RC3 SCK1 SCL1
0 1 0 1 0 1
O I O I O I O I I O I O I O O I O O I O I I O I
2
DIG ST DIG ST DIG DIG ST ST DIG DIG ST DIG DIG ST DIG DIG ST DIG ST ST DIG ST
I2C/SMB I2C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/SDA1
RC4 SDI1 SDA1
0 1 1 1 1 0 1
I C/SMB I2C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1
RC5 SDO1
0 0 1
RC6/TX/CK
RC6 TX CK
1 1 1
RC7/RX/DT
RC7 RX DT
0 1 1 1 1
Legend: Note 1: 2:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2CTM/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3. Enhanced PWM output is available only on PIC18F44J10/45J10 devices.
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TABLE 10-8:
Name PORTC LATC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Reset Values on page 50 50 50
PORTC Data Latch Register (Read and Write to Data Latch) PORTC Data Direction Control Register
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10.5
Note:
PORTD, TRISD and LATD Registers
PORTD is only available in 40/44-pin devices.
PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Three of the PORTD pins are multiplexed with outputs P1B, P1C and P1D of the Enhanced CCP module. The operation of these additional PWM output pins is covered in greater detail in Section 15.0 "Enhanced Capture/Compare/PWM (ECCP) Module". Note: On a Power-on Reset, these pins are configured as digital inputs.
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.7 "Parallel Slave Port" for additional information on the Parallel Slave Port (PSP). Note: When the Enhanced PWM mode is used with either dual or quad outputs, the PSP functions of PORTD are automatically disabled.
EXAMPLE 10-5:
CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTD
Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs
CLRF
LATD
MOVLW 0CFh
MOVWF TRISD
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TABLE 10-9:
Pin RD0/PSP0/SCK2/ SCL2
PORTD I/O SUMMARY
Function RD0 PSP0 SCK2 SCL2 TRIS Setting 0 1 x x 0 1 0 1 I/O O I O I O I O I O I O I I O I O I O I O O I O I I O I O I O I O I O O I O I O O I O I O I I/O Type DIG ST DIG TTL DIG ST DIG LATD<0> data output. PORTD<0> data input. PSP read data output (LATD<0>); takes priority over port data. PSP write data input. SPI clock output (MSSP2 module); takes priority over port data. SPI clock input (MSSP2 module). I2CTM clock output (MSSP2 module); takes priority over port data. Description
I2C/SMB I2C clock input (MSSP2 module); input type depends on module setting. DIG ST DIG TTL ST DIG
2C/SMB
RD1/PSP1/SDI2/ SDA2
RD1 PSP1 SDI2 SDA2
0 1 x x 1 1 1
LATD<1> data output. PORTD<1> data input. PSP read data output (LATD<1>); takes priority over port data. PSP write data input. SPI data input (MSSP2 module). I2C data output (MSSP2 module); takes priority over port data. I2C data input (MSSP2 module); input type depends on module setting. LATD<2> data output. PORTD<2> data input. PSP read data output (LATD<2>); takes priority over port data. PSP write data input. SPI data output (MSSP2 module); takes priority over port data. LATD<3> data output. PORTD<3> data input. PSP read data output (LATD<3>); takes priority over port data. PSP write data input. Slave select input for MSSP2 (MSSP2 module). LATD<4> data output. PORTD<4> data input. PSP read data output (LATD<4>); takes priority over port data. PSP write data input. LATD<5> data output. PORTD<5> data input. PSP read data output (LATD<5>); takes priority over port data. PSP write data input. ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. LATD<6> data output. PORTD<6> data input. PSP read data output (LATD<6>); takes priority over port data. PSP write data input. ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. LATD<7> data output. PORTD<7> data input. PSP read data output (LATD<7>); takes priority over port data. PSP write data input. ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events.
RD2/PSP2/SDO2
RD2 PSP2 SDO2
0 1 x x 0 0 1
DIG ST DIG TTL DIG DIG ST DIG TTL TTL DIG ST DIG TTL DIG ST DIG TTL DIG DIG ST DIG TTL DIG DIG ST DIG TTL DIG
RD3/PSP3/SS2
RD3 PSP3 SS2
x x 1 0 1
RD4/PSP4
RD4 PSP4
x x
RD5/PSP5/P1B
RD5 PSP5 P1B
0 1 x x 0 0 1
RD6/PSP6/P1C
RD6 PSP6 P1C
x x 0 0 1
RD7/PSP7/P1D
RD7 PSP7 P1D
x x 0
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2CTM/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option).
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TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name PORTD(1) LATD
(1)
Bit 7 RD7
Bit 6 RD6
Bit 5 RD5
Bit 4 RD4
Bit 3 RD3
Bit 2 RD2
Bit 1 RD1
Bit 0 RD0
Reset Values on page 50 50 50
PORTD Data Latch Register (Read and Write to Data Latch) PORTD Data Direction Control Register IBF P1M1(1) OBF P1M0(1) IBOV DC1B1 PSPMODE DC1B0 -- CCP1M3 TRISE2 CCP1M2 TRISE1 CCP1M1 TRISE0 CCP1M0
TRISD(1) TRISE
(1)
50 49
CCP1CON
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTD. Note 1: These registers and/or bits are not available in 28-pin devices.
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10.6
Note:
PORTE, TRISE and LATE Registers
PORTE is only available in 40/44-pin devices.
The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation is explained in Register 10-1. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE.
Depending on the particular PIC18F45J10 family device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as analog inputs, these pins will read as `0's. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE<2:0> are configured as analog inputs.
EXAMPLE 10-6:
CLRF PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTE
Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as inputs RE<1> as outputs RE<2> as inputs
CLRF
LATE
MOVLW MOVWF MOVLW
0Ah ADCON1 03h
MOVWF
TRISE
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REGISTER 10-1:
R-0 IBF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISE REGISTER (40/44-PIN DEVICES ONLY)
R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit 0
IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as `0' TRISE2: RE2 Direction Control bit 1 = Input 0 = Output TRISE1: RE1 Direction Control bit 1 = Input 0 = Output TRISE0: RE0 Direction Control bit 1 = Input 0 = Output
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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TABLE 10-11: PORTE I/O SUMMARY
Pin RE0/RD/AN5 Function RE0 RD AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS AN7 Legend: TRIS Setting 0 1 1 1 0 1 1 1 0 1 1 1 I/O O I I I O I I I O I I I I/O Type DIG ST TTL ANA DIG ST TTL ANA DIG ST TTL ANA Description LATE<0> data output; not affected by analog input. PORTE<0> data input; disabled when analog input enabled. PSP read enable input (PSP enabled). A/D Input Channel 5; default input configuration on POR. LATE<1> data output; not affected by analog input. PORTE<1> data input; disabled when analog input enabled. PSP write enable input (PSP enabled). A/D Input Channel 6; default input configuration on POR. LATE<2> data output; not affected by analog input. PORTE<2> data input; disabled when analog input enabled. PSP write enable input (PSP enabled). A/D Input Channel 7; default input configuration on POR.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name PORTE(1) LATE(1) TRISE(1) ADCON1 Bit 7 -- -- IBF -- Bit 6 -- -- OBF -- Bit 5 -- -- IBOV VCFG1 Bit 4 -- -- PSPMODE VCFG0 Bit 3 -- -- -- PCFG3 Bit 2 RE2 Bit 1 RE1 Bit 0 RE0 Reset Values on page 50 50 50 48
PORTE Data Latch Register (Read and Write to Data Latch) TRISE2 PCFG2 TRISE1 PCFG1 TRISE0 PCFG0
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTE. Note 1: These registers are not available in 28-pin devices.
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10.7
Note:
Parallel Slave Port
The Parallel Slave Port is only available in 40/44-pin devices.
The timing for the control signals in Write and Read modes is shown in Figure 10-4 and Figure 10-5, respectively.
In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation as long as the Enhanced CCP module is not operating in Dual Output or Quad Output PWM mode. In Slave mode, the port is asynchronously readable and writable by the external world. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE I/O pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PFCG<3:0> (ADCON1<3:0>), must also be set to a value in the range of `1010' through `1111'. A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is clear. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken.
FIGURE 10-3:
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
One bit of PORTD
Data Bus
D CK
Q RDx pin
WR LATD or WR PORTD
Data Latch Q D EN EN
TTL
RD PORTD
RD LATD
Set Interrupt Flag PSPIF (PIR1<7>)
PORTE Pins Read TTL RD CS WR
Chip Select TTL Write TTL
Note:
I/O pins have diode protection to VDD and VSS.
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FIGURE 10-4: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
FIGURE 10-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 10-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name PORTD(1) LATD(1) TRISD(1) PORTE LATE(1) TRISE(1) INTCON PIR1 PIE1 IPR1 ADCON1
(1)
Bit 7 RD7
Bit 6 RD6
Bit 5 RD5
Bit 4 RD4
Bit 3 RD3
Bit 2 RD2
Bit 1 RD1
Bit 0 RD0
Reset Values on page 50 50 50
PORTD Data Latch Register (Read and Write to Data Latch) PORTD Data Direction Control Register -- -- IBF PSPIF
(1)
-- -- OBF ADIF ADIE ADIP --
-- -- IBOV TMR0IE RCIF RCIE RCIP VCFG1
-- -- PSPMODE INT0IE TXIF TXIE TXIP VCFG0
-- -- -- RBIE SSP1IF SSP1IE SSP1IP PCFG3
RE2
RE1
RE0
50 50 50 47 49 49 49 48
PORTE Data Latch Register (Read and Write to Data Latch) TRISE2 TMR0IF CCP1IF CCP1IE CCP1IP PCFG2 TRISE1 INT0IF TMR2IF TMR2IE TMR2IP PCFG1 TRISE0 RBIF TMR1IF TMR1IE TMR1IP PCFG0
GIE/GIEH PEIE/GIEL PSPIE(1) PSPIP(1) --
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as `0'.
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11.0 TIMER0 MODULE
The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-bit or 16-bit modes * Readable and writable registers * Dedicated 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt-on-overflow The T0CON register (Register 11-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1. Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode.
REGISTER 11-1:
R/W-1 TMR0ON bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T0CON: TIMER0 CONTROL REGISTER
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0
R/W-1 T08BIT
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value
bit 6
bit 5
bit 4
bit 3
bit 2-0
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11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RB5/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter.
11.2
Timer0 Reads and Writes in 16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0 which is not directly readable nor writable (refer to Figure 11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4 0 1 1 Sync with Internal Clocks (2 TCY Delay) 8 8 Internal Data Bus TMR0L Set TMR0IF on Overflow
T0CKI pin T0SE T0CS T0PS<2:0> PSA
Programmable Prescaler 3
0
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
FOSC/4
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0 1 1 Sync with Internal Clocks (2 TCY Delay) Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus TMR0L TMR0 High Byte 8 Set TMR0IF on Overflow
T0CKI pin T0SE T0CS T0PS<2:0> PSA
Programmable Prescaler 3
0
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
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11.3 Prescaler
11.3.1
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution.
11.4
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep.
TABLE 11-1:
Name TMR0L TMR0H INTCON T0CON TRISA
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 48 48 INT0IE T0SE -- RBIE PSA TRISA3 TMR0IF T0PS2 TRISA2 INT0IF T0PS1 TRISA1 RBIF T0PS0 TRISA0 47 48 50 T0CS TRISA5
Timer0 Register Low Byte Timer0 Register High Byte GIE/GIEH PEIE/GIEL TMR0IE TMR0ON -- T08BIT --
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Timer0.
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NOTES:
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12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR1H and TMR1L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt-on-overflow * Reset on CCP Special Event Trigger * Device clock status flag (T1RUN) A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register (Register 12-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>).
REGISTER 12-1:
R/W-0 RD16 bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T1CON: TIMER1 CONTROL REGISTER
R-0 R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
T1RUN
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
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12.1 Timer1 Operation
Timer1 can operate in one of these modes: * Timer * Synchronous Counter * Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'.
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator On/Off Timer1 Clock Input 1 Prescaler 1, 2, 4, 8 0 2 T1OSCEN(1) T1CKPS<1:0> T1SYNC TMR1ON TMR1CS Sleep Input Timer1 On/Off Synchronize Detect 0 1 FOSC/4 Internal Clock
T1OSO/T1CKI
T1OSI
Clear TMR1 (CCP Special Event Trigger)
TMR1L
TMR1 High Byte
Set TMR1IF on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
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FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator T1OSO/T1CKI FOSC/4 Internal Clock T1OSCEN(1) T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 (CCP Special Event Trigger) TMR1 High Byte 8 Set TMR1IF on Overflow TMR1CS 1 Prescaler 1, 2, 4, 8 0 2 Sleep Input Timer1 On/Off Timer1 Clock Input 1 Synchronize Detect 0
T1OSI
TMR1L
Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
12.2
Timer1 16-Bit Read/Write Mode
12.3
Timer1 Oscillator
Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
An on-chip crystal oscillator circuit is incorporated between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL COMPONENTS FOR THE TIMER1 OSCILLATOR
PIC18F45J10
T1OSI XTAL 32.768 kHz T1OSO
C1 27 pF
C2 27 pF Note: See the Notes with Table 12-1 for additional information about capacitor selection.
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TABLE 12-1:
Oscillator Type LP
CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4)
Freq. 32 kHz C1 27 pF(1) C2 27 pF(1)
12.3.2
TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS
The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single-sided PCB or in addition to a ground plane.
Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only.
FIGURE 12-4:
OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING
VDD VSS OSC1 OSC2
12.3.1
USING TIMER1 AS A CLOCK SOURCE
The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS<1:0> (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 4.0 "Power-Managed Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source.
RC0 RC1
RC2 Note: Not drawn to scale.
12.4
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>).
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12.5 Resetting Timer1 Using the ECCP/CCP Special Event Trigger 12.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the one described in Section 12.3 "Timer1 Oscillator" above) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflows. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.
If ECCP1/CCP1 or CCP2 is configured to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer1. The trigger from CCP2 will also start an A/D conversion if the A/D module is enabled (see Section 15.2.1 "Special Event Trigger" for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRH:CCPRL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: The Special Event Triggers from the ECCP1/CCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>).
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EXAMPLE 12-1:
RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN RTCisr BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs secs mins, F .59 mins mins hours, F .23 hours hours ; ; ; ; ; ; ; ; ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? No, done Clear seconds Increment minutes 60 minutes elapsed? No, done clear minutes Increment hours 24 hours elapsed? 80h TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ;
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
; Enable Timer1 interrupt
; No, done ; Reset hours ; Done
TABLE 12-2:
Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSP1IF SSP1IE SSP1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on page 47 49 49 49 48 48 TMR1CS TMR1ON 48
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) ADIF ADIE ADIP
Timer1 Register Low Byte Timer1 Register High Byte RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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13.0 TIMER2 MODULE
13.1 Timer2 Operation
The Timer2 timer module incorporates the following features: * 8-bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2 to PR2 match * Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register (Register 13-1) which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 13-1. In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options; these are selected by the prescaler control bits, T2CKPS<1:>0 (T2CON<1:0>). The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 13.2 "Timer2 Interrupt"). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: * a write to the TMR2 register * a write to the T2CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.
REGISTER 13-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3
T2CON: TIMER2 CONTROL REGISTER
R/W-0 T2OUTPS2 R/W-0 T2OUTPS1 R/W-0 T2OUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
R/W-0 T2OUTPS3
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2
bit 1-0
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13.2 Timer2 Interrupt 13.3 Timer2 Output
Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 16.0 "Master Synchronous Serial Port (MSSP) Module".
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4 2 TMR2/PR2 Match Comparator
8
T2OUTPS<3:0> T2CKPS<1:0>
1:1 to 1:16 Postscaler
Set TMR2IF TMR2 Output (to PWM or MSSP)
FOSC/4
1:1, 1:4, 1:16 Prescaler
Reset TMR2
8
PR2
8
Internal Data Bus
TABLE 13-1:
Name
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSP1IF SSP1IE SSP1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on page 47 49 49 49 48 T2CKPS1 T2CKPS0 48 48
Bit 7
INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR2 T2CON PR2 PSPIF(1) PSPIE(1) PSPIP(1) -- ADIF ADIE ADIP
Timer2 Register T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON Timer2 Period Register
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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14.0 CAPTURE/COMPARE/PWM (CCP) MODULES
The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. Note: Throughout this section and Section 15.0 "Enhanced Capture/Compare/PWM (ECCP) Module", references to the register and bit names for CCP modules are referred to generically by the use of `x' or `y' in place of the specific module number. Thus, "CCPxCON" might refer to the control register for CCP1, CCP2 or ECCP1. "CCPxCON" is used throughout these sections to refer to the module control register regardless of whether the CCP module is a standard or Enhanced implementation.
PIC18F45J10 family devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter. In 40/44-pin devices, CCP1 is implemented as an Enhanced CCP module (ECCP1) with standard Capture and Compare modes and Enhanced PWM modes. The Enhanced CCP implementation is discussed in Section 15.0 "Enhanced Capture/Compare/PWM (ECCP) Module".
REGISTER 14-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
CCPxCON: CCP1/CCP2 CONTROL REGISTER IN 28-PIN DEVICES
U-0 -- R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL. CCPxM<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode
bit 3-0
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14.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. Both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. The interactions between the two modules are summarized in Figure 14-1 and Figure 14-2. In Timer1 in Asynchronous Counter mode, the capture operation will not work.
14.1.1
CCP MODULES AND TIMER RESOURCES
14.1.2
CCP2 PIN ASSIGNMENT
The CCP modules utilize Timers 1 or 2, depending on the mode selected. Timer1 is available to modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode.
The pin assignment for CCP2 (Capture input, Compare and PWM output) can change, based on device configuration. The CCP2MX Configuration bit determines which pin CCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the Configuration bit is cleared, CCP2 is multiplexed with RB3. Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation regardless of where it is located.
TABLE 14-1:
ECCP/CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
ECCP/CCP Mode Capture Compare PWM
TABLE 14-2:
Capture Capture
INTERACTIONS BETWEEN ECCP1/CCP1 AND CCP2 FOR TIMER RESOURCES
Interaction Each module uses TMR1 as the time base. CCP2 can be configured for the Special Event Trigger to reset TMR1. Automatic A/D conversions on the trigger event can also be done. Operation of ECCP1/CCP1 will be affected. ECCP1/CCP1 can be configured for the Special Event Trigger to reset TMR1. Operation of CCP2 will be affected. Either module can be configured for the Special Event Trigger to reset TMR1. Automatic A/D conversions on the CCP2 trigger event can be done. None None None None Both PWMs will have the same frequency and update rate (TMR2 interrupt). Capture Compare
CCP1 Mode CCP2 Mode
Compare Compare Capture Compare PWM(1) PWM
(1)
Capture Compare PWM(1) PWM
(1)
Capture Compare PWM
PWM(1) Note 1:
Includes standard and Enhanced PWM operation.
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14.2 Capture Mode
14.2.3 CCP PRESCALER
In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 register when an event occurs on the corresponding CCPx pin. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 14-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value is overwritten by the new captured value.
EXAMPLE 14-1:
14.2.1
CCP PIN CONFIGURATION
CLRF MOVLW CCP2CON NEW_CAPT_PS
CHANGING BETWEEN CAPTURE PRESCALERS (CCP2 SHOWN)
; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP2CON with this value
In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Note: If RB3/CCP2 or RC1/CCP2 is configured as an output, a write to the port can cause a capture condition.
MOVWF
CCP2CON
14.2.2
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode.
FIGURE 14-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF CCP1 pin Prescaler / 1, 4, 16 and Edge Detect TMR1H 4 4 4 TMR1L CCPR1H CCPR1L
CCP1CON<3:0> Q1:Q4 CCP2CON<3:0>
Set CCP2IF
CCP2 pin Prescaler / 1, 4, 16 and Edge Detect
CCPR2H
CCPR2L
TMR1H
TMR1L
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14.3 Compare Mode
14.3.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register value. When a match occurs, the CCPx pin can be: * * * * driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the I/O latch) Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
14.3.3
SOFTWARE INTERRUPT MODE
The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set.
When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the corresponding CCPx pin is not affected. Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set.
14.3.4
SPECIAL EVENT TRIGGER
14.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. Note: Clearing the CCP2CON register will force the RB3 or RC1 compare output latch (depending on device configuration) to the default low level. This is not the PORTB or PORTC I/O data latch.
Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCPxM<3:0> = 1011). For either CCP module, the Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module's time base. This allows the CCPRx registers to serve as a Programmable Period register for either timer. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled.
FIGURE 14-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF Special Event Trigger (Timer1 Reset) CCP1 pin Comparator Compare Match Output Logic 4 CCP1CON<3:0> S R TRIS Output Enable Q
CCPR1H
CCPR1L
TMR1H
TMR1L Special Event Trigger (Timer1 Reset, A/D Trigger)
Set CCP2IF Comparator Compare Match Output Logic 4 CCP2CON<3:0> S R Q
CCP2 pin
CCPR2H
CCPR2L
TRIS Output Enable
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TABLE 14-3:
Name INTCON RCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 TRISB TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE RI TXIF TXIE TXIP -- -- -- Bit 3 RBIE TO SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP -- -- -- Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP -- -- -- Bit 0 RBIF BOR TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values on page 47 46 49 49 49 49 49 49 50 50 48 48 TMR1CS TMR1ON 48 49 49 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49 49 49 CCP2M3 CCP2M2 CCP2M1 CCP2M0 49
GIE/GIEH PEIE/GIEL TMR0IE IPEN PSPIF(1) PSPIE
(1)
-- ADIF ADIE ADIP CMIF CMIE CMIP
CM RCIF RCIE RCIP -- -- --
PSPIP(1) OSCFIF OSCFIE OSCFIP
PORTB Data Direction Control Register PORTC Data Direction Control Register Timer1 Register Low Byte Timer1 Register High Byte RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte P1M1(1) P1M0(1) DC1B1 DC1B0 Capture/Compare/PWM Register 2 Low Byte Capture/Compare/PWM Register 2 High Byte -- -- DC2B1 DC2B0
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Capture/Compare or Timer1. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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14.4 PWM Mode
14.4.1 PWM PERIOD
In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force the RB3 or RC1 output latch (depending on device configuration) to the default low level. This is not the PORTB or PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
EQUATION 14-1:
PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set) * The PWM duty cycle is latched from CCPRxL into CCPRxH Note: The Timer2 postscalers (see Section 13.0 "Timer2 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 14-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 14.4.4 "Setup for PWM Operation".
FIGURE 14-3:
Duty Cycle Registers CCPRxL
SIMPLIFIED PWM BLOCK DIAGRAM
CCPxCON<5:4>
CCPRxH (Slave) CCPx Output Comparator R Q
14.4.2
PWM DUTY CYCLE
TMR2
(Note 1)
S Corresponding TRIS bit
Comparator
The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. The following equation is used to calculate the PWM duty cycle in time:
PR2
Clear Timer, CCP1 pin and latch D.C.
EQUATION 14-2:
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) * TOSC * (TMR2 Prescale Value) CCPRxL and CCPxCON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register.
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
A PWM output (Figure 14-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 14-4:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
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The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation:
EQUATION 14-3:
FOSC log --------------- FPWM PWM Resolution (max) = -----------------------------bits log ( 2 ) Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be cleared.
TABLE 14-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
14.4.3
PWM AUTO-SHUTDOWN (CCP1 ONLY)
14.4.4
SETUP FOR PWM OPERATION
The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 15.4.7 "Enhanced PWM Auto-Shutdown". Auto-shutdown features are not available for CCP2.
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits. Make the CCPx pin an output by clearing the appropriate TRIS bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCPx module for PWM operation.
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TABLE 14-5:
Name INTCON RCON PIR1 PIE1 IPR1 TRISB TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON ECCP1AS ECCP1DEL
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 Bit 6 Bit 5 TMR0IE CM RCIF RCIE RCIP Bit 4 INT0IE RI TXIF TXIE TXIP Bit 3 RBIE TO SSP1IF SSP1IE SSP1IP Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP Bit 0 RBIF BOR TMR1IF TMR1IE TMR1IP Reset Values on page 47 46 49 49 49 50 50 48 48 48 49 49 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49 49 49 CCP2M3 PSSAC1 PDC3(1) CCP2M2 PDC2(1) CCP2M1 PDC1(1) CCP2M0 PDC0(1) 49 49 49 PSSAC0 PSSBD1(1) PSSBD0(1)
GIE/GIEH PEIE/GIEL IPEN PSPIF(1) PSPIE
(1)
-- ADIF ADIE ADIP
PSPIP(1)
PORTB Data Direction Control Register PORTC Data Direction Control Register Timer2 Register Timer2 Period Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte P1M1(1) P1M0(1) DC1B1 DC1B0 Capture/Compare/PWM Register 2 Low Byte Capture/Compare/PWM Register 2 High Byte -- PRSEN -- PDC6(1) DC2B1 ECCPAS1 PDC5(1) DC2B0 ECCPAS0 PDC4(1) ECCPASE ECCPAS2
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PWM or Timer2. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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15.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE
The ECCP module is implemented only in 40/44-pin devices. and restart. The Enhanced features are discussed in detail in Section 15.4 "Enhanced PWM Mode". Capture, Compare and single output PWM functions of the ECCP module are the same as described for the standard CCP module. The control register for the Enhanced CCP module is shown in Register 15-1. It differs from the CCP1CON register in PIC18F24J10/25J10 devices in that the two Most Significant bits are implemented to control PWM functionality.
Note:
In PIC18F44J10/45J10 devices, ECCP1 is implemented as a standard CCP module with Enhanced PWM capabilities. These include the provisions for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown
REGISTER 15-1:
R/W-0 P1M1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
CCP1CON: ECCP1 CONTROL REGISTER (40/44-PIN DEVICES)
R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
R/W-0 P1M0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. CCP1M<3:0>: CCP1 Module Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP resets TMR1, sets CCP1IF bit) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
bit 5-4
bit 3-0
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In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features. It is: * ECCP1DEL (PWM Dead-Band Delay)
15.2
Capture and Compare Modes
15.1
ECCP Outputs and Configuration
Except for the operation of the Special Event Trigger discussed below, the Capture and Compare modes of the ECCP module are identical in operation to that of CCP2. These are discussed in detail in Section 14.2 "Capture Mode" and Section 14.3 "Compare Mode". No changes are required when moving between 28-pin and 40/44-pin devices.
The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC and PORTD. The outputs that are active depend on the ECCP operating mode selected. The pin assignments are summarized in Table 15-1. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M<1:0> and CCP1M<3:0> bits. The appropriate TRISC and TRISD direction bits for the port pins must also be set as outputs.
15.2.1
SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1.
15.3
Standard PWM Mode
15.1.1
ECCP MODULES AND TIMER RESOURCES
When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode, as described in Section 14.4 "PWM Mode". This is also sometimes referred to as "Compatible CCP" mode, as in Table 15-1. Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 14.4.4 "Setup for PWM Operation" or Section 15.4.9 "Setup for PWM Operation". The latter is more generic and will work for either single or multi-output PWM.
Like the standard CCP modules, the ECCP module can utilize Timers 1 or 2, depending on the mode selected. Timer1 is available for modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode. Interactions between the standard and Enhanced CCP modules are identical to those described for standard CCP modules. Additional details on timer resources are provided in Section 14.1.1 "CCP Modules and Timer Resources".
TABLE 15-1:
ECCP Mode
PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES
CCP1CON Configuration RC2 All 40/44-pin Devices: RD5 RD6 RD7
Compatible CCP Dual PWM Quad PWM
00xx 11xx 10xx 11xx x1xx 11xx
CCP1 P1A P1A
RD5/PSP5 P1B P1B
RD6/PSP6 RD6/PSP6 P1C
RD7/PSP7 RD7/PSP7 P1D
Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
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15.4 Enhanced PWM Mode
15.4.1 PWM PERIOD
The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the P1M<1:0> and CCP1M<3:0> bits of the CCP1CON register. Figure 15-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Dead-Band Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the period boundary (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation.
EQUATION 15-1:
PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 13.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
FIGURE 15-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4> P1M1<1:0> 2 CCP1M<3:0> 4 CCP1/P1A TRISx
Duty Cycle Registers CCPR1L
CCP1/P1A
CCPR1H (Slave) Comparator R Q
P1B Output Controller P1C TRISx
P1B
TMR2
(Note 1)
P1C TRISx
S P1D
Comparator
P1D TRISx
PR2
Clear Timer, set CCP1 pin and latch D.C. ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
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15.4.2 PWM DUTY CYCLE
Note: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L register contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
15.4.3
PWM OUTPUT CONFIGURATIONS
The P1M<1:0> bits in the CCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation:
The Single Output mode is the standard PWM mode discussed in Section 15.4 "Enhanced PWM Mode". The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 15-2.
EQUATION 15-3:
log FOSC FPWM PWM Resolution (max) = log(2)
(
) bits
TABLE 15-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
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FIGURE 15-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0 CCP1CON <7:6> SIGNAL Duty Cycle PR2 + 1 Period
00
(Single Output)
P1A Modulated Delay(1) P1A Modulated Delay(1)
10
(Half-Bridge)
P1B Modulated P1A Active
01
(Full-Bridge, Forward)
P1B Inactive P1C Inactive P1D Modulated P1A Inactive
11
(Full-Bridge, Reverse)
P1B Modulated P1C Active P1D Inactive
FIGURE 15-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
SIGNAL 0 Duty Cycle PR2 + 1 Period
CCP1CON <7:6>
00
(Single Output)
P1A Modulated P1A Modulated
10
(Half-Bridge)
Delay(1) P1B Modulated P1A Active
Delay(1)
01
(Full-Bridge, Forward)
P1B Inactive P1C Inactive P1D Modulated P1A Inactive
11
(Full-Bridge, Reverse)
P1B Modulated P1C Active P1D Inactive
Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 15.4.6 "Programmable Dead-Band Delay").
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15.4.4 HALF-BRIDGE MODE FIGURE 15-4:
Period Duty Cycle P1A(2) td P1B(2)
(1)
In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 15-4). This mode can be used for half-bridge applications, as shown in Figure 15-5, or for full-bridge applications where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, PDC<6:0>, sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 15.4.6 "Programmable Dead-Band Delay" for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs.
HALF-BRIDGE PWM OUTPUT
Period
td
(1)
(1)
td = Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high.
FIGURE 15-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit ("Push-Pull")
PIC18F4XJ10 P1A
FET Driver
+ V Load
FET Driver P1B
+ V -
VHalf-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F4XJ10 P1A Load
FET Driver
FET Driver
FET Driver P1B
FET Driver
V-
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15.4.5 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 15-6. P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs.
FIGURE 15-6:
Forward Mode
FULL-BRIDGE PWM OUTPUT
Period P1A
(2)
Duty Cycle P1B(2)
P1C(2)
P1D(2) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) (1)
P1D(2) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. (1)
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FIGURE 15-7: EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F4XJ10 P1A
FET Driver
QA
QC
FET Driver
P1B FET Driver
Load FET Driver
P1C
QB
QD
VP1D
15.4.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in the time interval, 4 TOSC * (Timer2 Prescale Value), before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS<1:0> bits (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 15-8. Note that in the Full-Bridge Output mode, the ECCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time.
Figure 15-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs P1A and P1D become inactive while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices, QC and QD (see Figure 15-7), for the duration of `t'. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on.
Other options to prevent shoot-through current may exist.
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FIGURE 15-8:
SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. (Note 2)
PWM DIRECTION CHANGE
Period(1) Period
FIGURE 15-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period t1 Reverse Period
P1A(1) P1B(1) P1C(1) P1D(1) DC
DC tON(2)
External Switch C(1) tOFF(3) External Switch D(1) Potential Shoot-Through Current(1) Note 1: 2: 3: All signals are shown as active-high. tON is the turn-on delay of power switch QC and its driver. tOFF is the turn-off delay of power switch QD and its driver. t = tOFF - tON(2,3)
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15.4.6
Note:
PROGRAMMABLE DEAD-BAND DELAY
Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules.
In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the nonactive state to the active state. See Figure 15-4 for an illustration. Bits PDC<6:0> of the ECCP1DEL register (Register 15-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). These bits are not available in 28-pin devices as the standard CCP module does not support half-bridge operation.
A shutdown event can be caused by either of the comparator modules, a low level on the Fault input pin (FLT0) or any combination of these three sources. The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a low digital signal on FLT0 can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The autoshutdown sources to be used are selected using the ECCPAS<2:0> bits (bits<6:4> of the ECCP1AS register). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC<1:0> and PSSBD<1:0> bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/ P1D) may be set to drive high, drive low or be tri-stated (not driving). The ECCPASE bit (ECCP1AS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active.
15.4.7
ENHANCED PWM AUTO-SHUTDOWN
When the ECCP1 is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs.
REGISTER 15-2:
R/W-0 PRSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
ECCP1DEL: PWM DEAD-BAND DELAY REGISTER
R/W-0 PDC5(1) R/W-0 PDC4(1) R/W-0 PDC3(1) R/W-0 PDC2(1) R/W-0 PDC1(1) R/W-0 PDC0(1) bit 0
R/W-0 PDC6(1)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM PDC<6:0>: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Reserved on 28-pin devices; maintain these bits clear.
bit 6-0
Note 1:
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REGISTER 15-3:
R/W-0 ECCPASE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER
R/W-0 ECCPAS1 R/W-0 ECCPAS0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1
(1)
R/W-0 ECCPAS2
R/W-0 PSSBD0(1) bit 0
ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits 111 = FLT0, Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled PSSAC<1:0>: Pins A and C Shutdown State Control bits 1x = Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices) 01 = Drive Pins A and C to `1' 00 = Drive Pins A and C to `0' PSSBD<1:0>: Pins B and D Shutdown State Control bits(1) 1x = Pins B and D tri-state 01 = Drive Pins B and D to `1' 00 = Drive Pins B and D to `0' Reserved on 28-pin devices; maintain these bits clear.
bit 6-4
bit 3-2
bit 1-0
Note 1:
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15.4.7.1 Auto-Shutdown and Automatic Restart 15.4.8 START-UP CONSIDERATIONS
The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 15-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared. If PRSEN = 0 (Figure 15-11), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. When the ECCP module is used in the PWM mode, the application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M<1:0> bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended, since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins.
Independent of the PRSEN bit setting, if the autoshutdown source is one of the comparators, the shutdown condition is a level. The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCPASE bit.
FIGURE 15-10:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Resumes
FIGURE 15-11:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes
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15.4.9 SETUP FOR PWM OPERATION 15.4.10
The following steps should be taken when configuring the ECCP module for PWM operation: Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. 2. Set the PWM period by loading the PR2 register. 3. If auto-shutdown is required: * Disable auto-shutdown (ECCPASE = 0) * Configure source (FLT0, Comparator 1 or Comparator 2) * Wait for non-shutdown condition 4. Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M<1:0> bits. * Select the polarities of the PWM output signals with the CCP1M<3:0> bits. 5. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. 6. For Half-Bridge Output mode, set the deadband delay by loading ECCP1DEL<6:0> with the appropriate value. 7. If auto-shutdown operation is required, load the ECCP1AS register: * Select the auto-shutdown sources using the ECCPAS<2:0> bits. * Select the shutdown states of the PWM output pins using the PSSAC<1:0> and PSSBD<1:0> bits. * Set the ECCPASE bit (ECCP1AS<7>). * Configure the comparators using the CMCON register. * Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: * Wait until TMRx overflows (TMRxIF bit is set). * Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. * Clear the ECCPASE bit (ECCP1AS<7>). 1.
OPERATION IN POWER-MANAGED MODES
In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other power-managed modes, the selected power-managed mode clock will clock Timer2. Other power-managed mode clocks will most likely be different than the primary clock frequency.
15.4.10.1
Operation with Fail-Safe Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure will force the device into the power-managed RC_RUN mode and the OSCFIF bit (PIR2<7>) will be set. The ECCP will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. See the previous section for additional details.
15.4.11
EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module.
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TABLE 15-3:
Name INTCON RCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 TRISB TRISC TRISD(1) TMR1L TMR1H T1CON TMR2 T2CON PR2 CCPR1L CCPR1H CCP1CON ECCP1AS ECCP1DEL Legend: Note 1:
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1
Bit 7 Bit 6 Bit 5 TMR0IE CM RCIF RCIE RCIP -- -- -- Bit 4 INT0IE RI TXIF TXIE TXIP -- -- -- Bit 3 RBIE TO SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF PD CCP1IF CCP1IE CCP1IP -- -- -- Bit 1 INT0IF POR TMR2IF TMR2IE TMR2IP -- -- -- Bit 0 RBIF BOR TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values on page 47 46 49 49 49 49 49 49 50 50 50 48 48 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48 48 48 48 49 49 CCP1M3 PSSAC1 PDC3
(1)
GIE/GIEH PEIE/GIEL IPEN PSPIF(1) PSPIE(1) PSPIP(1) OSCFIF OSCFIE OSCFIP -- ADIF ADIE ADIP CMIF CMIE CMIP
PORTB Data Direction Control Register PORTC Data Direction Control Register PORTD Data Direction Control Register Timer1 Register Low Byte Timer1 Register High Byte RD16 -- T1RUN Timer2 Register T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer2 Period Register Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte P1M1(1) PRSEN P1M0(1) PDC6
(1)
DC1B1 ECCPAS1 PDC5
(1)
DC1B0 ECCPAS0 PDC4
(1)
CCP1M2 PSSAC0 PDC2
(1)
CCP1M1 PDC1(1)
CCP1M0 PDC0(1)
49 49 49
ECCPASE ECCPAS2
PSSBD1(1) PSSBD0(1)
-- = unimplemented, read as `0'. Shaded cells are not used during ECCP operation. These registers and/or bits are not implemented on 28-pin devices and should be read as `0'.
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16.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
Master SSP (MSSP) Module Overview
Note: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCON register names. SSP1CON1 and SSP1CON2 control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules.
16.1
The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode PIC18F24J10/25J10 (28-pin) devices have one MSSP module designated as MSSP1. PIC18F44J10/45J10 (40/44-pin) devices have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. Note: Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator `x' to indicate the use of a numeral to distinguish a particular module, when required. Control bit names are not individuated.
16.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDOx) - RC5/SDO1 or RD2/PSP2/SDO2 * Serial Data In (SDIx) - RC4/SDI1/SDA1 or RD1/PSP1/SDI2/SDA2 * Serial Clock (SCKx) - RC3/SCK1/SCL1 or RD0/PSP0/SCK2/SCL2 Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SSx) - RA5/AN4/SS1/C2OUT or RD3/PSP3/SS2 Figure 16-1 shows the block diagram of the MSSP module when operating in SPI mode.
FIGURE 16-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPxBUF reg Write
SDIx SSPxSR reg SDOx bit 0 Shift Clock
16.2
Control Registers
Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. Note: Disabling the MSSP module by clearing the SSPEN (SSPxCON1<5>) bit may not reset the module. It is recommended to clear the SSPxSTAT, SSPxCON1 and SSPxCON2 registers and select the mode prior to setting the SSPEN bit to enable the MSSP module.
SSx
SSx Control Enable Edge Select 2 Clock Select SSPM<3:0> SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64
(
)
SCKx
Data to TX/RX in SSPxSR TRIS bit Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions.
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16.3.1 REGISTERS
Each MSSP module has four registers for SPI mode operation. These are: * MSSP Control Register 1 (SSPxCON1) * MSSP Status Register (SSPxSTAT) * Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSP Shift Register (SSPxSR) - Not directly accessible SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR.
REGISTER 16-1:
R/W-0 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
(1)
R/W-0 CKE
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state D/A: Data/Address bit Used in I2C mode only. P: Stop bit Used in I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared. S: Start bit Used in I2C mode only. R/W: Read/Write Information bit Used in I2C mode only. UA: Update Address bit Used in I2C mode only. BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
bit 6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Note 1:
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REGISTER 16-2:
R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
R/W-0 SSPEN
(2)
R/W-0 SSPOV
(1)
R/W-0 CKP
R/W-0 SSPM3
(3)
R/W-0 SSPM2
(3)
R/W-0 SSPM1
(3)
R/W-0 SSPM0(3) bit 0
WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. Bit combinations not specifically listed here are either reserved or implemented in I2CTM mode only.
bit 6
bit 5
bit 4
bit 3-0
Note 1: 2: 3:
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16.3.2 OPERATION
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) Each MSSP consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full detect bit, BF (SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the * * * * SSPxBUF register during transmission/reception of data will be ignored and the Write Collision detect bit, WCOL (SSPxCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPxBUF register completed successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF (SSPxSTAT<0>), indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPxBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 16-1 shows the loading of the SSP1BUF (SSP1SR) for data transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions.
EXAMPLE 16-1:
LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF
LOADING THE SSP1BUF (SSP1SR) REGISTER
SSP1STAT, BF LOOP SSP1BUF, W RXDATA TXDATA, W SSP1BUF ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSP1BUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
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16.3.3 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDIx is automatically controlled by the SPI module * SDOx must have TRISC<5> (or TRISD<2>) bit cleared * SCKx (Master mode) must have TRISC<3> (or TRISD<0>) bit cleared * SCKx (Slave mode) must have TRISC<3> (or TRISD<0>) bit set * SSx must have TRISA<5> (or TRISD<3>) bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.
16.3.4
TYPICAL CONNECTION
Figure 16-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCKx signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data
FIGURE 16-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xxb SDOx SDIx
SPI Slave SSPM<3:0> = 010xb
Serial Input Buffer (SSPxBUF)
Serial Input Buffer (SSPxBUF)
Shift Register (SSPxSR) MSb LSb
SDIx
SDOx
Shift Register (SSPxSR) MSb LSb
SCKx PROCESSOR 1
Serial Clock
SCKx PROCESSOR 2
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16.3.5 MASTER MODE
The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 16-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 16-3, Figure 16-5 and Figure 16-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 16-3 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown.
FIGURE 16-3:
Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) SDOx (CKE = 1) SDIx (SMP = 0) Input Sample (SMP = 0) SDIx (SMP = 1) Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF
SPI MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit 7 bit 7
bit 6 bit 6
bit 5 bit 5
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1
bit 0 bit 0
bit 7
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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16.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit (SSPxCON1<4>). While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SSx pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can be connected to the SDIx pin. When the SPI needs to operate as a receiver, the SDOx pin can be configured as an input. This disables transmissions from the SDOx. The SDIx can always be left as an input (SDIx function) since it cannot create a bus conflict.
16.3.7
SLAVE SELECT SYNCHRONIZATION
The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 04h). When the SSx pin is low, transmission and reception are enabled and the
FIGURE 16-4:
SSx
SLAVE SYNCHRONIZATION WAVEFORM
SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0)
Write to SSPxBUF
SDOx
bit 7
bit 6
bit 7
bit 0
SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF
bit 0 bit 7 bit 7
Next Q4 Cycle after Q2
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FIGURE 16-5:
SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit 7
bit 0
Next Q4 Cycle after Q2
FIGURE 16-6:
SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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16.3.8 OPERATION IN POWER-MANAGED MODES 16.3.10 BUS MODE COMPATIBILITY
In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 3.6 "Clock Sources and Oscillator Switching" for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. Table 16-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
TABLE 16-1:
SPI BUS MODES
Control Bits State CKP 0 0 1 1 CKE 1 0 1 0
Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1
There is also an SMP bit which controls when the data is sampled.
16.3.11
SPI CLOCK SPEED AND MODULE INTERACTIONS
Because MSSP1 and MSSP2 are independent modules, they can operate simultaneously at different data rates. Setting the SSPM<3:0> bits of the SSPxCON1 register determines the rate for the corresponding module. An exception is when both modules use Timer2 as a time base in Master mode. In this instance, any changes to the Timer2 operation will affect both MSSP modules equally. If different bit rates are required for each module, the user should select one of the other three time base options for one of the modules.
16.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the current transfer.
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TABLE 16-2:
Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 TRISA TRISC TRISD(1) SSP1BUF SSP1CON1 SSP1STAT SSP2BUF SSP2CON1 SSP2STAT
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP -- -- -- -- TRISC4 TRISD4 CKP P CKP P Bit 3 RBIE SSP1IF SSP1IE SSP1IP -- -- -- TRISA3 TRISC3 TRISD3 SSPM3 S SSPM3 S Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP -- -- -- TRISA2 TRISC2 TRISD2 SSPM2 R/W SSPM2 R/W Bit 1 INT0IF TMR2IF TMR2IE TMR2IP -- -- -- TRISA1 TRISC1 TRISD1 SSPM1 UA SSPM1 UA Bit 0 RBIF TMR1IF TMR1IE TMR1IP -- -- -- TRISA0 TRISC0 TRISD0 SSPM0 BF SSPM0 BF Reset Values on page 47 49 49 49 49 49 49 50 50 50 48 48 48 50 50 50
GIE/GIEH PEIE/GIEL TMR0IE PSPIF(1) PSPIE PSPIP
(1) (1)
ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP -- TRISC6 TRISD6 SSPOV CKE SSPOV CKE
RCIF RCIE RCIP -- -- -- TRISA5 TRISC5 TRISD5 SSPEN D/A SSPEN D/A
SSP2IF SSP2IE SSP2IP -- TRISC7 TRISD7 WCOL SMP WCOL SMP
MSSP1 Receive Buffer/Transmit Register
MSSP2 Receive Buffer/Transmit Register
Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as `0'.
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16.4 I2C Mode
16.4.1 REGISTERS
The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCLx) - RC3/SCK1/SCL1 or RD6/SCK2/SCL2 * Serial data (SDAx) - RC4/SDI1/SDA1 or RD5/SDI2/SDA2 The user must configure these pins as inputs by setting the associated TRIS bits. The MSSP module has six registers for I2C operation. These are: * * * * MSSP Control Register 1 (SSPxCON1) MSSP Control Register 2 (SSPxCON2) MSSP Status Register (SSPxSTAT) Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSP Shift Register (SSPxSR) - Not directly accessible * MSSP Address Register (SSPxADD) SSPxCON1, SSPxCON2 and SSPxSTAT are the control and status registers in I2C mode operation. The SSPxCON1 and SSPxCON2 registers are readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. Many of the bits in SSPxCON2 assume different functions, depending on whether the module is operating in Master or Slave mode; bits<5:2> also assume different names in Slave mode. The different aspects of SSPxCON2 are shown in Register 16-5 (for Master mode) and Register 16-6 (Slave mode). SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. SSPxADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value. In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Note: Disabling the MSSP module by clearing the SSPEN (SSPxCON1<5>) bit may not reset the module. It is recommended to clear the SSPxSTAT, SSPxCON1 and SSPxCON2 registers and select the mode prior to setting the SSPEN bit to enable the MSSP module.
FIGURE 16-7:
MSSP BLOCK DIAGRAM (I2CTM MODE)
Internal Data Bus
Read SCLx Shift Clock SSPxSR reg SDAx MSb SSPxBUF reg
Write
LSb Addr Match
Match Detect Address Mask
SSPxADD reg
Start and Stop bit Detect
Set, Reset S, P bits (SSPxSTAT reg)
Note:
Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions.
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REGISTER 16-3:
R/W-0 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPxSTAT: MSSPx STATUS REGISTER (I2CTM MODE)
R-0 D/A R-0 P
(1)
R/W-0 CKE
R-0 S
(1)
R-0 R/W
R0 UA
R-0 BF bit 0
SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last R/W: Read/Write Information bit (I2C mode only) In Slave mode:(2) 1 = Read 0 = Write In Master mode:(3) 1 = Transmit is in progress 0 = Transmit is not in progress UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) This bit is cleared on Reset and when SSPEN is cleared. This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2: 3:
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REGISTER 16-4:
R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPxCON1: MSSPx CONTROL REGISTER 1 (I2CTM MODE)
R/W-0 SSPEN
(1)
R/W-0 SSPOV
R/W-0 CKP
R/W-0 SSPM3
R/W-0 SSPM2
R/W-0 SSPM1
R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. When enabled, the SDAx and SCLx pins must be configured as inputs.
bit 6
bit 5
bit 4
bit 3-0
Note 1:
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REGISTER 16-5:
R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPxCON2: MSSPx CONTROL REGISTER 2 (I2CTM MASTER MODE)
R/W-0 ACKDT
(1)
R/W-0 ACKSTAT
R/W-0 ACKEN
(2)
R/W-0 RCEN
(2)
R/W-0 PEN
(2)
R/W-0 RSEN
(2)
R/W-0 SEN(2) bit 0
GCEN: General Call Enable bit Unused in Master mode. ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle PEN: Stop Condition Enable bit(2) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enable bit(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Start Condition Enable bit(2) 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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REGISTER 16-6:
R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPxCON2: MSSPx CONTROL REGISTER 2 (I2CTM SLAVE MODE)
R/W-0 ADMSK5 R/W-0 ADMSK4 R/W-0 ADMSK3 R/W-0 ADMSK2 R/W-0 ADMSK1 R/W-0 SEN(1) bit 0
R/W-0 ACKSTAT
GCEN: General Call Enable bit 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit Unused in Slave mode. ADMSK<5:2>: Slave Address Mask Select bits 1 = Masking of corresponding bits of SSPxADD enabled 0 = Masking of corresponding bits of SSPxADD disabled ADMSK1: Slave Address Least Significant bit(s) Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> only enabled 0 = Masking of SSPxADD<1> only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> enabled 0 = Masking of SSPxADD<1:0> disabled SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
bit 6 bit 5-2
bit 1
bit 0
Note 1:
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16.4.2 OPERATION
The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the operation. Four mode selection (SSPxCON1<3:0>) allow one of the following modes to be selected: * I2C Master mode, clock = (FOSC/4) x (SSPxADD + 1) * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled * I 2C Firmware Controlled Master mode, slave is Idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCLx and SDAx pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC or TRISD bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCLx and SDAx pins. I 2C bits I 2C The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101.
16.4.3.1
Addressing
Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the clock (SCLx) line. The value of register SSPxSR<7:1> is compared to the value of the SSPxADD register. The address is compared on the falling edge of the eighth clock (SCLx) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPxSR register value is loaded into the SSPxBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. The MSSP Interrupt Flag bit, SSPxIF, is set (and interrupt is generated, if enabled) on the falling edge of the ninth SCLx pulse.
16.4.3
SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an exact address match. In addition, address masking will also allow the hardware to generate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and Stop bits. When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPxBUF register with the received value currently in the SSPxSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The Buffer Full bit, BF (SSPxSTAT<0>), was set before the transfer was received. * The MSSP Overflow bit, SSPOV (SSPxCON1<6>), was set before the transfer was received. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but the SSPxIF bit is set. The BF bit is cleared by reading the SSPxBUF register, while the SSPOV bit is cleared through software.
In 10-Bit Addressing mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPxSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-Bit Addressing mode is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. Receive first (high) byte of address (bits, SSPxIF, BF and UA (SSPxSTAT<1>), are set). Update the SSPxADD register with second (low) byte of address (clears bit, UA, and releases the SCLx line). Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. Receive second (low) byte of address (bits, SSPxIF, BF and UA, are set). Update the SSPxADD register with the first (high) byte of address. If match releases SCLx line, this will clear bit, UA. Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. Receive Repeated Start condition. Receive first (high) byte of address (bits, SSPxIF and BF, are set). Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF.
3. 4. 5.
6. 7. 8. 9.
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16.4.3.2 Address Masking
Masking an address bit causes that bit to become a "don't care". When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-Bit Addressing mode and up to 63 addresses in 10-Bit Addressing mode (see Example 16-2). The I2C Slave behaves the same way, whether address masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking SSPxBUF. In 7-Bit Addressing mode, Address Mask bits, ADMSK<5:1> (SSPxCON2<5:1>), mask the corresponding address bits in the SSPxADD register. For any ADMSK bits that are set (ADMSK = 1), the corresponding address bit is ignored (SSPxADD = x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask. In 10-Bit Addressing mode, ADMSK<5:2> bits mask the corresponding address bits in the SSPxADD register. In addition, ADMSK1 simultaneously masks the two LSbs of the address (SSPxADD<1:0>). For any ADMSK bits that are active (ADMSK = 1), the corresponding address bit is ignored (SSPxADD = x). Also note that although in 10-Bit Addressing mode, the upper address bits reuse part of the SSPxADD register bits, the address mask bits do not interact with those bits. They only affect the lower address bits. Note 1: ADMSK1 masks the two Least Significant bits of the address. 2: The two Most Significant bits of the address are not affected by address masking.
EXAMPLE 16-2:
7-Bit Addressing:
ADDRESS MASKING EXAMPLES
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be `0') ADMSK<5:1> 10-Bit Addressing: SSPxADD<7:0>= A0h (10100000) (the two MSbs of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
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16.4.3.3 Reception 16.4.3.4 Transmission
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set, or bit, SSPOV (SSPxCON1<6>), is set. An MSSP interrupt is generated for each data transfer byte. The interrupt flag bit, SSPxIF, must be cleared in software. The SSPxSTAT register is used to determine the status of the byte. If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx (RC3 or RD0) will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPxCON1<4>). See Section 16.4.4 "Clock Stretching" for more details. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register. The ACK pulse will be sent on the ninth bit and pin RC3 or RD6 is held low, regardless of SEN (see Section 16.4.4 "Clock Stretching" for more details). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then pin RC3 or RD0 should be enabled by setting bit, CKP (SSPxCON1<4>). The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time (Figure 16-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. If the SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin RC3 or RD0 must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse.
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FIGURE 16-8:
(c) 2009 Microchip Technology Inc.
Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 R/W = 0 Receiving Data ACK Receiving Data D2 D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPxBUF is read SSPOV is set because SSPxBUF is still full. ACK is not sent.
SDAx
A7
A6
SCLx
S
1
2
SSPxIF (PIR1<3> or PIR3<7>)
BF (SSPxSTAT<0>)
SSPOV (SSPxCON1<6>)
CKP
I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING)
(CKP does not reset to `0' when SEN = 0)
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FIGURE 16-9:
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R/W = 0 ACK D1 D0 D4 D3 D2 D5 D7 D6 D1 Transmitting Data D0 A1 D3 D2 ACK D5 D4 D7 D6 Transmitting Data ACK A4 A2 A3 4 9 SCLx held low while CPU responds to SSPxIF 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software SSPxBUF is written in software Clear by reading From SSPxIF ISR Cleared in software SSPxBUF is written in software From SSPxIF ISR
Receiving Address
SDAx
A7
A6
A5
SCLx
S
1
2
3
Data in sampled
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SSPxIF (PIR1<3> or PIR3<7>)
BF (SSPxSTAT<0>)
CKP (SSPxCON<4>)
I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING)
(c) 2009 Microchip Technology Inc.
CKP is set in software
CKP is set in software
FIGURE 16-10:
Clock is held low until update of SSPxADD has taken place R/W = 0 A8 ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0
Clock is held low until update of SSPxADD has taken place ACK
Receive First Byte of Address 0 A9
(c) 2009 Microchip Technology Inc.
5 1 2 3 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPxBUF to clear BF flag SSPOV is set because SSPxBUF is still full. ACK is not sent. Cleared by hardware when SSPxADD is updated with low byte of address UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address
SDAx
1
1
1
1
SCLx
S
1
2
3
4
SSPxIF (PIR1<3> or PIR3<7>)
Cleared in software
BF (SSPxSTAT<0>)
SSPxBUF is written with contents of SSPxSR
SSPOV (SSPxCON1<6>)
UA (SSPxSTAT<1>)
UA is set indicating that the SSPxADD needs to be updated
CKP
I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING)
(CKP does not reset to `0' when SEN = 0)
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DS39682E-page 169
FIGURE 16-11:
DS39682E-page 170
Clock is held low until update of SSPxADD has taken place Clock is held low until CKP is set to `1' R/W = 1 ACK D7 D6 D5 Transmitting Data Byte D4 D3 D2 D1 D0 ACK R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPxADD has taken place Bus master terminates transfer 4 Sr 6 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPxBUF to clear BF flag Dummy read of SSPxBUF to clear BF flag Write of SSPxBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPxADD is updated with low byte of address UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address. CKP is set in software CKP is automatically cleared in hardware, holding SCLx low
Receive First Byte of Address
SDAx
1
1
1
SCLx
S
1
2
3
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SSPxIF (PIR1<3> or PIR3<7>)
BF (SSPxSTAT<0>)
SSPxBUF is written with contents of SSPxSR
UA (SSPxSTAT<1>)
UA is set indicating that the SSPxADD needs to be updated
I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING)
CKP (SSPxCON1<4>)
(c) 2009 Microchip Technology Inc.
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16.4.4 CLOCK STRETCHING 16.4.4.3
Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence.
Clock Stretching for 7-Bit Slave Transmit Mode
The 7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and load the contents of the SSPxBUF before the master device can initiate another transmit sequence (see Figure 16-9). Note 1: If the user loads the contents of SSPxBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit.
16.4.4.1
Clock Stretching for 7-Bit Slave Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPxCON1 register is automatically cleared, forcing the SCLx output to be held low. The CKP being cleared to `0' will assert the SCLx line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and read the contents of the SSPxBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 16-13). Note 1: If the user reads the contents of the SSPxBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition.
16.4.4.4
Clock Stretching for 10-Bit Slave Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 16-11).
16.4.4.2
Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs and if the user hasn't cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.
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DS39682E-page 171
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16.4.4.5 Clock Synchronization and the CKP bit
When the CKP bit is cleared, the SCLx output is forced to `0'. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 16-12).
FIGURE 16-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
DX
DX - 1
SCLx
CKP
Master Device Asserts Clock Master Device Deasserts Clock
WR SSPxCON
DS39682E-page 172
(c) 2009 Microchip Technology Inc.
FIGURE 16-13:
(c) 2009 Microchip Technology Inc.
Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK D2 D1 D0 D7 D6 D5 D4 Receiving Data D3 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software SSPxBUF is read SSPOV is set because SSPxBUF is still full. ACK is not sent. If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs CKP written to `1' in software
SDAx
A7
A6
SCLx
S
1
2
SSPxIF (PIR1<3> or PIR3<7>)
BF (SSPxSTAT<0>)
SSPOV (SSPxCON1<6>)
I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING)
CKP
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DS39682E-page 173
FIGURE 16-14:
DS39682E-page 174
Clock is held low until update of SSPxADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D0 D7 D6 D5 D4 D3 D2 ACK D1 D0 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte ACK Clock is held low until update of SSPxADD has taken place Clock is not held low because ACK = 1 A9 A8 6 1 2 3 4 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus master terminates transfer Dummy read of SSPxBUF to clear BF flag Dummy read of SSPxBUF to clear BF flag SSPOV is set because SSPxBUF is still full. ACK is not sent. Cleared by hardware when SSPxADD is updated with low byte of address after falling edge of ninth clock UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with high byte of address after falling edge of ninth clock Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. CKP written to `1' in software
Receive First Byte of Address
SDAx
1
1
1
1
0
SCLx
S
1
2
3
4
5
SSPxIF (PIR1<3> or PIR3<7>)
Cleared in software
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BF (SSPxSTAT<0>)
SSPxBUF is written with contents of SSPxSR
SSPOV (SSPxCON1<6>)
UA (SSPxSTAT<1>)
UA is set indicating that the SSPxADD needs to be updated
CKP
I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING)
(c) 2009 Microchip Technology Inc.
Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
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16.4.5 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPxCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPxBUF. The value can be used to determine if the address was device-specific or a general call address. In 10-bit mode, the SSPxADD is required to be updated for the second half of the address to match and the UA bit is set (SSPxSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 16-15).
FIGURE 16-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 D6 Receiving Data D5 D4 D3 D2 D1 D0 ACK
SDAx SCLx S SSPxIF BF (SSPxSTAT<0>)
General Call Address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) GCEN (SSPxCON2<7>) `1' `0'
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DS39682E-page 175
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16.4.6 MASTER MODE
Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDAx and SCLx. Assert a Repeated Start condition on SDAx and SCLx. Write to the SSPxBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur.
The following events will cause the MSSP Interrupt Flag bit, SSPxIF, to be set (and MSSP interrupt, if enabled): * * * * * Start condition Stop condition Data transfer byte transmitted/received Acknowledge transmit Repeated Start
FIGURE 16-16:
MSSP BLOCK DIAGRAM (I2CTM MASTER MODE)
Internal Data Bus Read SSPxBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) (c) 2009 Microchip Technology Inc. Shift Clock SSPxSR Receive Enable MSb LSb SSPM<3:0> SSPxADD<6:0>
SDAx
SDAx In
SCLx
SCLx In Bus Collision
Start bit Detect, Stop bit Detect, Write Collision Detect, Clock Arbitration, State Counter for End of XMIT/RCV
Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1); Set SSPxIF, BCLxIF; Reset ACKSTAT, PEN (SSPxCON2)
DS39682E-page 176
Clock Cntl
Start bit, Stop bit, Acknowledge Generate
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16.4.6.1 I2C Master Mode Operation
A typical transmit sequence would go as follows: The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2<0>). 2. SSPxIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPxBUF with the slave address to transmit. 4. Address is shifted out the SDAx pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 7. The user loads the SSPxBUF with eight bits of data. 8. Data is shifted out the SDAx pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPxCON2<2>). 12. Interrupt is generated once the Stop condition is complete. 1. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCLx clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 16.4.7 "Baud Rate" for more detail.
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16.4.7
2
BAUD RATE
In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 16-17). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to `0' and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state.
Table 16-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.
16.4.7.1
Baud Rate and Module Interdependence
Because MSSP1 and MSSP2 are independent, they can operate simultaneously in I2C Master mode at different baud rates. This is done by using different BRG reload values for each module. Because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. It may be possible to change one or both baud rates back to a previous value by changing the BRG reload value.
FIGURE 16-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0> SSPxADD<6:0>
SSPM<3:0> SCLx
Reload Control CLKO
Reload
BRG Down Counter
FOSC/4
TABLE 16-3:
FCY
I2CTM CLOCK RATE w/BRG
FCY * 2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz
2
BRG Value 18h 1Fh 63h 09h 0Ch 27h 02h 09h 00h
FSCL (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100 kHz 1 MHz(1)
10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz Note 1:
2
The I CTM interface does not conform to the 400 kHz I C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS39682E-page 178
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16.4.7.2 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 16-18).
FIGURE 16-18:
SDAx
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX SCLx deasserted but slave holds SCLx low (clock arbitration) DX - 1 SCLx allowed to transition high
SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h
SCLx is sampled high, reload takes place and BRG starts its count BRG Reload
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DS39682E-page 179
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16.4.8 I2C MASTER MODE START CONDITION TIMING
Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit (SSPxSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPxCON2<0>) will be automatically cleared by hardware. The Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. If, at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs. The Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state.
16.4.8.1
WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete.
FIGURE 16-19:
FIRST START BIT TIMING
Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) SDAx = 1, SCLx = 1 At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit TBRG Write to SSPxBUF occurs here 1st bit TBRG TBRG S 2nd bit
TBRG
SDAx
SCLx
DS39682E-page 180
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16.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING
Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPxIF bit getting set, the user may write the SSPxBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<6:0> and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. Following this, the RSEN bit (SSPxCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit (SSPxSTAT<3>) will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
16.4.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete.
FIGURE 16-20:
REPEATED START CONDITION WAVEFORM
S bit set by hardware SDAx = 1, SCLx = 1
TBRG TBRG TBRG
Write to SSPxCON2 occurs here: SDAx = 1, SCLx (no change)
At completion of Start bit, hardware clears RSEN bit and sets SSPxIF
SDAx RSEN bit set by hardware on falling edge of ninth clock, end of Xmit SCLx
TBRG
1st bit
Write to SSPxBUF occurs here
TBRG
Sr = Repeated Start
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DS39682E-page 181
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16.4.10 I2C MASTER MODE TRANSMISSION
Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification parameter 106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCLx is released high (see data setup time specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 16-21). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPxCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. The user should verify that the WCOL is clear after each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software.
16.4.10.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.
16.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPxCON2<3>). Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded.
The Baud Rate Generator begins counting, and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>).
16.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read.
16.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception.
16.4.10.1
BF Status Flag
16.4.11.3
WCOL Status Flag
In Transmit mode, the BF bit (SSPxSTAT<0>) is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out.
16.4.10.2
WCOL Status Flag
If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
If the user writes to the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur) after 2 TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer.
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FIGURE 16-21:
Write SSPxCON2<0> (SEN = 1) Start condition begins From slave, clear ACKSTAT bit (SSPxCON2<6>)
R/W = 0
ACKSTAT in SSPxCON2 = 1
(c) 2009 Microchip Technology Inc.
SEN = 0 Transmit Address to Slave SDAx A7 SSPxBUF written with 7-bit address and R/W start transmit SCLx S 1 2 3 4 5 6 7 8 9 1 SCLx held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 Transmitting Data or Second Half of 10-bit Address D1 D0 ACK SSPxIF Cleared in software Cleared in software service routine from MSSP interrupt Cleared in software BF (SSPxSTAT<0>) SSPxBUF written SEN After Start condition, SEN cleared by hardware SSPxBUF is written in software PEN R/W
I2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESSING)
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FIGURE 16-22:
DS39682E-page 184
Write to SSPxCON2<4> to start Acknowledge sequence SDAx = ACKDT (SSPxCON2<5>) = 0 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically Receiving Data from Slave ACK Receiving Data from Slave RCEN = 1, start next receive RCEN cleared automatically ACK ACK from Master, SDAx = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDAx = ACKDT = 1 PEN bit = 1 written here R/W = 1
Write to SSPxCON2<0> (SEN = 1), begin Start condition
SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT
Transmit Address to Slave
SDAx D0
A7 A1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2
ACK ACK is not sent Bus master terminates transfer
SCLx
Set SSPxIF interrupt at end of receive
S
1 5 1 2 3 4 5 1 2 3 4 5
2
3 4 8 6 7 8 9
6
7 9
6
7
8
9
Set SSPxIF at end of receive
P
Set SSPxIF interrupt at end of Acknowledge sequence
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Data shifted in on falling edge of CLK
SSPxIF
Cleared in software Cleared in software
Set SSPxIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software
SDAx = 0, SCLx = 1 while CPU responds to SSPxIF
Cleared in software
Set P bit (SSPxSTAT<4>) and SSPxIF
BF (SSPxSTAT<0>)
Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF
SSPOV
SSPOV is set because SSPxBUF is still full
I 2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING)
(c) 2009 Microchip Technology Inc.
ACKEN
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16.4.12 ACKNOWLEDGE SEQUENCE TIMING 16.4.13 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 16-23). A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to 0. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 16-24).
16.4.13.1
WCOL Status Flag
16.4.12.1
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur).
If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
FIGURE 16-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG SDAx D0 ACK TBRG ACKEN automatically cleared
SCLx
8
9
SSPxIF Cleared in software SSPxIF set at the end of Acknowledge sequence
SSPxIF set at the end of receive Note: TBRG = one Baud Rate Generator period.
Cleared in software
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FIGURE 16-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set TBRG Write to SSPxCON2, set PEN Falling edge of 9th clock SCLx
SDAx
ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition
Note: TBRG = one Baud Rate Generator period.
16.4.14
SLEEP OPERATION
I2C
16.4.17
While in Sleep mode, the module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled).
MULTI-MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION
16.4.15
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the current transfer.
16.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPxSTAT<4>) is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx, by letting SDAx float high, and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 16-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared.
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FIGURE 16-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master SDAx Sample SDAx. While SCLx is high, data doesn't match what is driven by the master. Bus collision has occurred.
SCLx
Set bus collision interrupt (BCLxIF)
BCLxIF
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16.4.17.1 Bus Collision During a Start Condition
During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 16-26). SCLx is sampled low before SDAx is asserted low (Figure 16-27). If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 16-28). If, however, a `1' is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to 0. If the SCLx pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions.
During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: * the Start condition is aborted; * the BCLxIF flag is set; and * the MSSP module is reset to its Idle state (Figure 16-26). The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded from SSPxADD<6:0> and counts down to `0'. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data `1' during the Start condition.
FIGURE 16-26:
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1.
SDAx
SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SEN cleared automatically because of bus collision. MSSP module reset into Idle state.
BCLxIF
SSPxIF SSPxIF and BCLxIF are cleared in software
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FIGURE 16-27: BUS COLLISION DURING START CONDITION (SCLx = 0)
SDAx = 0, SCLx = 1
TBRG TBRG
SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S SSPxIF `0' `0' `0' `0'
SCLx
SEN
FIGURE 16-28:
BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1 Set S Less than TBRG TBRG Set SSPxIF
SDAx
SDAx pulled low by other master. Reset BRG and assert SDAx.
SCLx
S
SCLx pulled low after BRG time-out Set SEN, enable Start sequence if SDAx = 1, SCLx = 1
SEN
BCLxIF
`0'
S
SSPxIF SDAx = 0, SCLx = 1, set SSPxIF Interrupts cleared in software
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16.4.17.2 Bus Collision During a Repeated Start Condition
During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', see Figure 16-29). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition (see Figure 16-30). If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete.
When the user deasserts SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD<6:0> and counts down to 0. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled.
FIGURE 16-29:
SDAx
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN
BCLxIF Cleared in software S SSPxIF `0' `0'
FIGURE 16-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDAx SCLx SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software
BCLxIF
RSEN S SSPxIF
`0'
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16.4.17.3 Bus Collision During a Stop Condition
Bus collision occurs during a Stop condition if: a) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 16-31). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 16-32).
b)
FIGURE 16-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF
SDAx SDAx asserted low SCLx PEN BCLxIF P SSPxIF
`0' `0'
FIGURE 16-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDAx Assert SDAx SCLx PEN BCLxIF P SSPxIF `0' `0' SCLx goes low before SDAx goes high, set BCLxIF
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TABLE 16-4:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 TRISC TRISD(1) SSP1BUF SSP1ADD SSP1CON1 SSP1CON2 SSP1STAT SSP2BUF SSP2ADD SSP2CON1 SSP2CON2 SSP2STAT Legend: Note 1: 2:
REGISTERS ASSOCIATED WITH I2CTM OPERATION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- -- -- -- TRISC5 TRISD5 Bit 4 INT0IE TXIF TXIE TXIP -- -- -- -- -- -- TRISC4 TRISD4 Bit 3 RBIE SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP -- -- -- TRISC3 TRISD3 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP -- -- -- -- -- -- TRISC2 TRISD2 Bit 1 INT0IF TMR2IF TMR2IE TMR2IP -- -- -- -- -- -- TRISC1 TRISD1 Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP -- -- -- TRISC0 TRISD0 Reset Values on Page 47 49 49 49 49 49 49 49 49 49 50 50 48 48 SSPM2 PEN ADMSK2(2) R/W SSPM1 RSEN ADMSK1(2) UA SSPM0 SEN SEN BF 48 48 48 48 50 50 SSPM2 PEN ADMSK2(2) R/W SSPM1 RSEN ADMSK1(2) UA SSPM0 SEN SEN BF 50 50 48 50
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE PSPIP
(1) (1)
ADIF ADIE ADIP CMIF CMIE CMIP BCL2IF BCL2IE BCL2IP TRISC6 TRISD6
OSCFIF OSCFIE OSCFIP SSP2IF SSP2IE SSP2IP TRISC7 TRISD7
MSSP1 Receive Buffer/Transmit Register MSSP1 Address Register (I2CTM Slave mode). MSSP1 Baud Rate Reload Register (I2C Master mode). WCOL GCEN GCEN SMP SSPOV ACKSTAT ACKSTAT CKE SSPEN ACKDT ADMSK5(2) D/A CKP ACKEN ADMSK4(2) P SSPM3 RCEN ADMSK3(2) S
MSSP2 Receive Buffer/Transmit Register MSSP2 Address Register (I2C Slave mode). MSSP2 Baud Rate Reload Register (I2C Master mode). WCOL GCEN GCEN SMP SSPOV ACKSTAT ACKSTAT CKE SSPEN ACKDT ADMSK5(2) D/A CKP ACKEN ADMSK4(2) P SSPM3 RCEN ADMSK3(2) S
-- = unimplemented, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. These registers and/or bits are not implemented on 28-pin devices and should be read as `0'. Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See Section 16.4.3.2 "Address Masking" for details.
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17.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as an EUSART: * bit SPEN (RCSTA<7>) must be set (= 1) * bit TRISC<7> must be set (= 1) * bit TRISC<6> must be set (= 1) Note: The EUSART control will automatically reconfigure the pin from input to output as needed.
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex, asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a halfduplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network (LIN/J2602) bus systems. The EUSART can be configured in the following modes: * Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission * Synchronous - Master (half duplex) with selectable clock polarity * Synchronous - Slave (half duplex) with selectable clock polarity
The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These are detailed on the following pages in Register 17-1, Register 17-2 and Register 17-3, respectively.
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REGISTER 17-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXSTA: EUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 TXEN(1) R/W-0 SYNC R/W-0 SENDB R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 TX9
R/W-0
CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th Bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 17-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: EUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 RX9
R/W-0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care. FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error RX9D: 9th Bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 17-3:
R/W-0 ABDOVF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BAUDCON: BAUD RATE CONTROL REGISTER 1
R-1 U-0 -- R/W-0 SCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0
RCIDL
ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator - SPBRG only (Compatible mode), SPBRGH value ignored Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode.
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
DS39682E-page 196
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17.1 Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also control the baud rate. In Synchronous mode, BRGH is ignored. Table 17-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 17-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 17-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 17-2. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
17.1.1
OPERATION IN POWER-MANAGED MODES
The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRG register pair.
17.1.2
SAMPLING
The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 17-1:
SYNC 0 0 0 0 1 1
BAUD RATE FORMULAS
BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x BRG/EUSART Mode 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n + 1)] Baud Rate Formula FOSC/[64 (n + 1)] FOSC/[16 (n + 1)]
Configuration Bits
Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair
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EXAMPLE 17-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16%
TABLE 17-2:
Name TXSTA RCSTA SPBRGH SPBRG
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 RCIDL Bit 5 TXEN SREN -- Bit 4 SYNC CREN SCKP Bit 3 SENDB ADDEN BRG16 Bit 2 BRGH FERR -- Bit 1 TRMT OERR WUE Bit 0 TX9D RX9D ABDEN Reset Values on page 49 49 49 49 49
BAUDCON ABDOVF
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG.
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TABLE 17-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate (K) -- 1.221 2.404 9.766 19.531 62.500 104.167 % Error -- 1.73 0.16 1.73 1.73 8.51 -9.58 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- 1.202 2.404 9.766 19.531 52.083 78.125 % Error -- 0.16 0.16 1.73 1.73 -9.58 -32.18 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- -- 255 64 31 10 4
-- 255 129 31 15 4 2
-- 129 64 15 7 2 1
-- 103 51 12 -- -- --
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 8.929 20.833 62.500 62.500 % Error 0.16 0.16 0.16 -6.99 8.51 8.51 -45.75 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 -- -- -- -- -- % Error -0.16 -0.16 -- -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
207 51 25 6 2 0 0
103 25 12 -- -- -- --
51 12 -- -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) -- -- -- 9.766 19.231 58.140 113.636 % Error -- -- -- 1.73 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) -- -- -- 9.615 19.231 56.818 113.636 % Error -- -- -- 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- -- 2.403 9.615 19.230 55.555 -- % Error -- -- -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- -- -- 255 129 42 21
-- -- -- 129 64 21 10
-- -- 255 64 31 10 4
-- -- 207 51 25 8 --
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) -- 1.202 2.404 9.615 19.231 62.500 125.000 % Error -- 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- 207 103 25 12 3 1
-- 103 51 12 -- -- --
207 51 25 -- -- -- --
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TABLE 17-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.399 9.615 19.231 56.818 113.636 % Error 0.02 -0.03 -0.03 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.531 56.818 125.000 % Error 0.02 -0.03 0.16 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
8332 2082 1040 259 129 42 21
4165 1041 520 129 64 21 10
2082 520 259 64 31 10 4
1665 415 207 51 25 8 --
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 9.615 19.231 62.500 125.000 % Error 0.04 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 -- -- -- % Error -0.16 -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
832 207 103 25 12 3 1
415 103 51 12 -- -- --
207 51 25 -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.606 19.193 57.803 114.943 % Error 0.00 0.00 0.02 0.06 -0.03 0.35 -0.22 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.596 19.231 57.471 116.279 % Error 0.00 0.02 0.02 -0.03 0.16 -0.22 0.94 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.615 19.230 57.142 117.647 % Error -0.01 -0.04 -0.04 -0.16 -0.16 0.79 -2.12 SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
33332 8332 4165 1040 520 172 86
16665 4165 2082 520 259 86 42
8332 2082 1040 259 129 42 21
6665 1665 832 207 103 34 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.231 58.824 111.111 % Error 0.01 0.04 0.16 0.16 0.16 2.12 -3.55 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 -- -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
3332 832 415 103 51 16 8
1665 415 207 51 25 8 --
832 207 103 25 12 -- --
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17.1.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 17-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN/J2602 bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCON<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 17-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table 17-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature.
TABLE 17-4:
BRG16 0 0 1 1 Note: BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Counter Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of BRG16 setting.
17.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation.
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FIGURE 17-1:
BRG Value RX pin
AUTOMATIC BAUD RATE CALCULATION
XXXXh 0000h Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 001Ch Edge #5 Stop Bit
BRG Clock Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH XXXXh XXXXh 1Ch 00h Auto-Cleared
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 17-2:
BRG Clock ABDEN bit RX pin ABDOVF bit
BRG OVERFLOW SEQUENCE
Start
Bit 0
FFFFh BRG Value XXXXh 0000h 0000h
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17.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software. TXIF is also not cleared immediately upon loading TXREG, but becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. Enable the transmission by setting bit, TXEN, which will also set bit, TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
2. 3. 4. 5. 6. 7. 8.
17.2.1
EUSART ASYNCHRONOUS TRANSMITTER
The EUSART transmitter block diagram is shown in Figure 17-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available).
FIGURE 17-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPEN *** TSR Register LSb 0 Pin Buffer and Control TX pin
TXIE
BRG16
SPBRGH
SPBRG
TX9 TX9D
Baud Rate Generator
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FIGURE 17-4:
Write to TXREG BRG Output (Shift Clock) TX (pin) TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 17-5:
Write to TXREG
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Word 1 Word 2
BRG Output (Shift Clock) TX (pin) TXIF bit (Interrupt Reg. Flag) 1 TCY 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0
TRMT bit (Transmit Shift Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 17-5:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 47 49 49 49 49 49 49 49 49 49
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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17.2.2 EUSART ASYNCHRONOUS RECEIVER 17.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
The receiver block diagram is shown in Figure 17-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 3. If interrupts are desired, set enable bit, RCIE. 4. If 9-bit reception is desired, set bit, RX9. 5. Enable the reception by setting bit, CREN. 6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCIE, was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 1. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU.
FIGURE 17-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN x64 Baud Rate CLK OERR FERR
BRG16
SPBRGH
SPBRG
Baud Rate Generator
/ 64 or / 16 or /4
MSb Stop (8) 7
RSR Register *** 1 0
LSb Start
RX9 Pin Buffer and Control RX Data Recovery RX9D RCREG Register FIFO
SPEN 8 Interrupt RCIF RCIE Data Bus
(c) 2009 Microchip Technology Inc.
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FIGURE 17-7:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (Overrun) bit to be set.
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
TABLE 17-6:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 47 49 49 49 49 49 49 49 49 49
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
17.2.4
AUTO-WAKE-UP ON SYNC BREAK CHARACTER
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 support protocol.)
Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 17-8) and asynchronously, if the device is in Sleep mode (Figure 17-9). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-tohigh transition is observed on the RX line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over.
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17.2.4.1 Special Considerations Using Auto-Wake-up 17.2.4.2 Special Considerations Using the WUE Bit
Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-OfCharacter (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.
FIGURE 17-8:
OSC1 WUE bit(1) RX/DT Line RCIF
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Auto-Cleared
Cleared due to user read of RCREG
Note 1:
The EUSART remains in Idle while the WUE bit is set.
FIGURE 17-9:
OSC1 WUE bit(2) RX/DT Line RCIF
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Auto-Cleared
Note 1 Sleep Ends Cleared due to user read of RCREG
Sleep Command Executed Note 1: 2:
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.
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17.2.5 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 support standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN/J2602 support). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 17-10 for the timing of the Break character sequence. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
17.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 17.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed.
17.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN bus master.
FIGURE 17-10:
Write to TXREG BRG Output (Shift Clock) TX (pin)
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Start Bit
Bit 0
Bit 1 Break
Bit 11
Stop Bit
TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here SENDB (Transmit Shift Reg. Empty Flag) Auto-Cleared
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17.3 EUSART Synchronous Master Mode
Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the TX and RX pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCON<4>). Setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module.
17.3.1
EUSART SYNCHRONOUS MASTER TRANSMISSION
2. 3. 4. 5. 6. 7. 8.
The EUSART transmitter block diagram is shown in Figure 17-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available).
FIGURE 17-11:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 bit 0 bit 1 bit 7
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1'
bit 0
bit 1
bit 2
Word 1
Word 2
Write Word 1
Write Word 2
`1'
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
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FIGURE 17-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7 RC7/RX/DT pin
RC6/TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 17-7:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 47 49 49 49 49 49 49 49 49 49 --
GIE/GIEH PEIE/GIEL TMR0IE PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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17.3.2 EUSART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 3. 4. 5. 6.
2.
FIGURE 17-13:
RC7/RX/DT pin RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RXREG Note:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 17-8:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN -- Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 47 49 49 49 49 49 49 49 49 49
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Receive Register
BAUDCON ABDOVF
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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17.4 EUSART Synchronous Slave Mode
To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. Clear bits, CREN and SREN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting enable bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode.
2. 3. 4. 5. 6. 7. 8.
17.4.1
EUSART SYNCHRONOUS SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. Flag bit, TXIF, will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector.
e)
TABLE 17-9:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 47 49 49 49 49 49 49 49 49 49 --
GIE/GIEH PEIE/GIEL TMR0IE PSPIF
(1)
ADIF ADIE ADIP RX9 TX9 RCIDL
RCIF RCIE RCIP SREN TXEN
PSPIE(1) PSPIP(1) SPEN CSRC ABDOVF
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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17.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION
To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. If interrupts are desired, set enable bit, RCIE. If 9-bit reception is desired, set bit, RX9. To enable reception, set enable bit, CREN. Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit, CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector.
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCON SPBRGH SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC SCKP Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADDEN SENDB BRG16 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on page 47 49 49 49 49 49 49 49 49 49 --
GIE/GIEH PEIE/GIEL TMR0IE PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Note 1: These bits are not implemented on 28-pin devices and should be read as `0'.
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NOTES:
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18.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The ADCON0 register, shown in Register 18-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 18-2, configures the functions of the port pins. The ADCON2 register, shown in Register 18-3, configures the A/D clock source, programmed acquisition time and justification.
The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2)
REGISTER 18-1:
R/W-0 ADCAL bit 7 Legend: R = Readable bit -n = Value at POR bit 7
ADCON0: A/D CONTROL REGISTER 0
U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D converter operation (no calibration is performed) Unimplemented: Read as `0' CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled These channels are not implemented on 28-pin devices. Performing a conversion on unimplemented channels will return a floating input measurement.
bit 6 bit 5-2
bit 1
bit 0
Note 1: 2:
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REGISTER 18-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: A/D CONTROL REGISTER 1
U-0 -- R/W-0 VCFG1 R/W-0 VCFG0 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
Unimplemented: Read as `0' VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD PCFG<3:0>: A/D Port Configuration Control bits: AN7(1) AN6(1) AN5(1) AN12 AN10 AN11 AN9 AN8 AN4 AN3 AN2 AN1 A A A A A A A A A A A A A A D D AN0 A A A A A A A A A A A A A A A D
bit 4
bit 3-0
PCFG<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note 1:
A A A D D D D D D D D D D D D D
A A A A D D D D D D D D D D D D
A A A A A D D D D D D D D D D D
A A A A A A D D D D D D D D D D
A A A A A A A D D D D D D D D D
A A A A A A A A D D D D D D D D
A A A A A A A A A D D D D D D D
A A A A A A A A A A D D D D D D
A A A A A A A A A A A D D D D D
A A A A A A A A A A A A D D D D
A A A A A A A A A A A A A D D D
A = Analog input
D = Digital I/O
AN5 through AN7 are available only on 40/44-pin devices.
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REGISTER 18-3:
R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON2: A/D CONTROL REGISTER 2
U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0
ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
bit 6 bit 5-3
bit 2-0
Note 1:
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The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 18-1.
FIGURE 18-1:
A/D BLOCK DIAGRAM
CHS<3:0> 1100 1011 1010 1001 1000 0111 0110 0101 0100 VAIN AN12 AN11 AN10 AN9 AN8 AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0
10-Bit A/D Converter
(Input Voltage)
0011 0010
VCFG<1:0> VDD(2) Reference Voltage VREF+ VREFX0 X1
0001 0000
1X 0X VSS(2)
Note 1: 2:
Channels AN5 through AN7 are not available in 28-pin devices. I/O pins have diode protection to VDD and VSS.
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After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 18.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) 6. 7. 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts.
3. 4. 5.
FIGURE 18-2:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS
RS
ANx
VAIN
CPIN 5 pF VT = 0.6V
ILEAKAGE 100 nA
CHOLD = 25 pF
VSS
Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance
VDD
1 2 3 4 Sampling Switch (k)
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18.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 18-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 18-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Equation 18-3 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 3V Rss = 2 k 85C (system max.)
EQUATION 18-1:
TACQ = =
ACQUISITION TIME
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF
EQUATION 18-2:
VHOLD or TC = =
A/D MINIMUM CHARGING TIME
(VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 18-3:
TACQ TAMP TCOFF = = = 0.2 s
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s 0.2 s + 1 s + 1.2 s 2.4 s
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC =
TACQ
=
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18.2 Selecting and Configuring Automatic Acquisition Time
TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES
Maximum Device Frequency 2.86 MHz 5.71 MHz 11.43 MHz 22.86 MHz 40.0 MHz 40.0 MHz 1.00 MHz(1) AD Clock Source (TAD) Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(2) ADCS<2:0> 000 100 001 101 010 110 x11
The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits (ADCON2<5:3>) remain in their Reset state (`000') and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun.
Note 1: The RC source has a typical TAD time of 4 s. 2: For device frequencies above 1 MHz, the device must be in Sleep mode for the entire conversion or the A/D accuracy may be out of specification.
18.4
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<3:0> bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits.
18.3
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table 24-25 for more information). Table 18-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
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18.5 A/D Conversions 18.6 Use of the ECCP2 Trigger
Figure 18-3 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 18-4 shows the operation of the A/D converter after the GO/DONE bit has been set, the ACQT<2:0> bits are set to `010' and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. An A/D conversion can be started by the "Special Event Trigger" of the ECCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time is selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter.
FIGURE 18-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 18-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQT Cycles 1 2 3 4 1 2 b9 3 b8 4 b7
TAD Cycles 5 b6 6 b5 7 b4 8 b3 9 b2 10 b1 11 b0
Automatic Acquisition Time
Conversion starts (Holding capacitor is disconnected)
Set GO/DONE bit (Holding capacitor continues acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input.
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18.7 A/D Converter Calibration
The A/D converter in the PIC18F45J10 family of devices includes a self-calibration feature which compensates for any offset generated within the module. The calibration process is automated and is initiated by setting the ADCAL bit (ADCON0<7>). The next time the GO/DONE bit is set, the module will perform a "dummy" conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for offset. Thus, subsequent offsets will be compensated. The calibration process assumes that the device is in a relatively steady-state operating condition. If A/D calibration is used, it should be performed after each device Reset or if there are other major changes in operating conditions. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Sleep mode requires the A/D RC clock to be selected. If bits, ACQT<2:0>, are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion.
18.8
Operation in Power-Managed Modes
The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode.
TABLE 18-2:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA PORTB TRISB LATB PORTE(1) TRISE(1) LATE
(1)
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- Bit 4 INT0IE TXIF TXIE TXIP -- -- -- Bit 3 RBIE SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP -- -- -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP -- -- -- Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values on page 47 49 49 49 49 49 49 48 48 CHS2 VCFG0 ACQT1 -- -- RB4 CHS1 PCFG3 ACQT0 RA3 TRISA3 RB3 CHS0 PCFG2 ADCS2 RA2 TRISA2 RB2 GO/DONE PCFG1 ADCS1 RA1 TRISA1 RB1 ADON PCFG0 ADCS0 RA0 TRISA0 RB0 48 48 48 50 50 50 50 50 RE2 TRISE2 RE1 TRISE1 RE0 TRISE0 50 50 50 -- PSPMODE -- -- -- --
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) OSCFIF OSCFIE OSCFIP ADIF ADIE ADIP CMIF CMIE CMIP
A/D Result Register High Byte A/D Result Register Low Byte ADCAL -- ADFM -- -- RB7 -- -- -- -- -- RB6 CHS3 VCFG1 ACQT2 RA5 TRISA5 RB5
PORTB Data Direction Control Register PORTB Data Latch Register (Read and Write to Data Latch) -- IBF -- -- OBF -- -- IBOV --
PORTE Data Latch Register (Read and Write to Data Latch)
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as `0'.
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19.0 COMPARATOR MODULE
The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section 20.0 "Comparator Voltage Reference Module"). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. The CMCON register (Register 19.1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations are shown in Figure 19-1.
REGISTER 19-1:
R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7
CMCON: COMPARATOR CONTROL REGISTER
R-0 R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-1 CM2 R/W-1 CM1 R/W-1 CM0 bit 0
C1OUT
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RA3/AN3/VREF+ C2 VIN- connects to RA2/AN2/VREF-/CVREF 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 CM<2:0>: Comparator Mode bits Figure 19-1 shows the Comparator modes and the CM<2:0> bit settings.
bit 6
bit 5
bit 4
bit 3
bit 2-0
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19.1 Comparator Configuration
There are eight modes of operation for the comparators, shown in Figure 19-1. Bits, CM<2:0> of the CMCON register, are used to select these modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 24.0 "Electrical Characteristics". Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur.
FIGURE 19-1:
Comparators Reset CM<2:0> = 000 RA0/AN0
A
COMPARATOR I/O OPERATING MODES
Comparators Off (POR Default Value) CM<2:0> = 111
VINVIN+
RA0/AN0 C1 Off (Read as `0') RA3/AN3/ VREF+ RA1/AN1 C2 Off (Read as `0')
D D
VINVIN+
RA3/AN3/ A VREF+ RA1/AN1
A
C1
Off (Read as `0')
VINVIN+
D
VINVIN+
RA2/AN2/ A VREF-/CVREF
D RA2/AN2/ VREF-/CVREF
C2
Off (Read as `0')
Two Independent Comparators CM<2:0> = 010 RA0/AN0
A VINVIN+
Two Independent Comparators with Outputs CM<2:0> = 011 RA0/AN0
A VINVIN+
RA3/AN3/ A VREF+ RA1/AN1
A
C1
C1OUT
VINVIN+
RA3/AN3/ A VREF+ RB5/KBI1/ T0CKI/C1OUT* RA1/AN1
A
C1
C1OUT
RA2/AN2/ A VREF-/CVREF
C2
C2OUT
VINVIN+
RA2/AN2/ A VREF-/CVREF
C2
C2OUT
RA5/AN4/SS1/C2OUT* Two Common Reference Comparators CM<2:0> = 100 RA0/AN0
A VINVIN+
Two Common Reference Comparators with Outputs CM<2:0> = 101 RA0/AN0
A VINVIN+
RA3/AN3/ A VREF+ RA1/AN1
A
C1
C1OUT
VINVIN+
A RA3/AN3/ VREF+ RB5/KBI1/ T0CKI/C1OUT*
C1
C1OUT
RA2/AN2/ D VREF-/CVREF
C2
C2OUT
RA1/AN1
A
VINVIN+
D RA2/AN2/ VREF-/CVREF
C2
C2OUT
RA5/AN4/SS1/C2OUT* One Independent Comparator with Output CM<2:0> = 001 RA0/AN0
A VINVIN+
Four Inputs Multiplexed to Two Comparators CM<2:0> = 110 RA0/AN0
A A CIS = 0 CIS = 1 VINVIN+
RA3/AN3/ A VREF+
C1
C1OUT
RA3/AN3/ VREF+ RA1/AN1
C1
C1OUT
RB5/KBI1/T0CKI/C1OUT* RA1/AN1
D VINVIN+
A CIS = 0 CIS = 1 VINVIN+
RA2/AN2/ D VREF-/CVREF/
C2
Off (Read as `0')
A RA2/AN2/ VREF-/CVREF/
C2
C2OUT
CVREF
From VREF Module
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5> bit will disable the comparator outputs by configuring the pins as inputs.
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19.2 Comparator Operation
19.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 19-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 19-2 represent the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. This module is described in more detail in Section 20.0 "Comparator Voltage Reference Module". The internal reference is only available in the mode where four inputs are multiplexed to two comparators (CM<2:0> = 110). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
19.3
Comparator Reference
19.4
Comparator Response Time
Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 19-2).
FIGURE 19-2:
SINGLE COMPARATOR
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section 24.0 "Electrical Characteristics").
19.5
VIN+ VIN-
Comparator Outputs
+ -
Output
VINVIN+
The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RB5 and RA5 I/O pins. When enabled, multiplexors in the output path of the RB5 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 19-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RB5 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>).
Output
19.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s).
Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
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FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM
MULTIPLEX
Port Pins
+
To RB5 or RA5 pin D CxINV EN Q Bus Data
Read CMCON
-
D EN Reset
Q CL From Other Comparator
Set CMIF bit
19.6
Comparator Interrupts
19.7
The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR2<6>) is the Comparator Interrupt Flag. The CMIF bit must be reset by clearing it. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR2 register) interrupt flag may not get set.
Comparator Operation During Sleep
When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CM<2:0> = 111) before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected.
19.8
Effects of a Reset
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF.
A device Reset forces the CMCON register to its Reset state, causing the comparator modules to be turned off (CM<2:0> = 111). However, the input pins (RA0 through RA3) are configured as analog inputs by default on device Reset. The I/O configuration for these pins is determined by the setting of the PCFG<3:0> bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset time.
A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared.
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19.9 Analog Input Connection Considerations
range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
A simplified circuit for an analog input is shown in Figure 19-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this
FIGURE 19-4:
COMPARATOR ANALOG INPUT MODEL
VDD RS < 10k AIN VT = 0.6V RIC Comparator Input CPIN 5 pF VT = 0.6V ILEAKAGE 100 nA
VA
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage
TABLE 19-1:
Name CMCON CVRCON INTCON PIR2 PIE2 IPR2 PORTA LATA TRISA
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 C2OUT CVREN OSCFIF OSCFIE OSCFIP -- -- -- Bit 6 C1OUT CVROE CMIF CMIE CMIP -- -- -- Bit 5 C2INV CVRR TMR0IE -- -- -- RA5 TRISA5 Bit 4 C1INV CVRSS INT0IE -- -- -- -- -- Bit 3 CIS CVR3 RBIE BCL1IF BCL1IE BCL1IP RA3 TRISA3 Bit 2 CM2 CVR2 TMR0IF -- -- -- RA2 TRISA2 Bit 1 CM1 CVR1 INT0IF -- -- -- RA1 TRISA1 Bit 0 CM0 CVR0 RBIF CCP2IF CCP2IE CCP2IP RA0 TRISA0 Reset Values on page 49 49 50 49 49 49 50 50 50
GIE/GIEH PEIE/GIEL
PORTA Data Latch Register (Read and Write to Data Latch)
Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the comparator module.
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20.0 COMPARATOR VOLTAGE REFERENCE MODULE
used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR<3:0>)/24) x CVRSRC If CVRR = 0: CVREF = (CVRSRC x 1/4) + (((CVR<3:0>)/32) x CVRSRC) The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 24-3 in Section 24.0 "Electrical Characteristics").
The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 20-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference.
20.1
Configuring the Comparator Voltage Reference
The voltage reference module is controlled through the CVRCON register (Register 20-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be
REGISTER 20-1:
R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0
(1)
R/W-0 CVROE
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator reference source, CVRSRC = VDD - VSS CVR<3:0>: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) * (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) * (CVRSRC) CVROE overrides the TRISA<2> bit setting.
bit 6
bit 5
bit 4
bit 3-0
Note 1:
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FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ VDD CVRSS = 1
CVRSS = 0
8R R R R
CVR<3:0>
CVREN
16 Steps
16-to-1 MUX
R
CVREF
R R R CVRR VREFCVRSS = 1
8R
CVRSS = 0
20.2
Voltage Reference Accuracy/Error
20.4
Effects of a Reset
The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 20-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 24.0 "Electrical Characteristics".
A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit, CVROE (CVRCON<6>) and selects the high-voltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared.
20.5
Connection Considerations
20.3
Operation During Sleep
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the CVROE bit is set. Enabling the voltage reference output onto RA2 when it is configured as a digital input will increase current consumption. Connecting RA2 as a digital output with CVRSS enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 20-2 shows an example buffering technique.
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FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F45J10
CVREF Module R(1) Voltage Reference Output Impedance RA2
+ -
CVREF Output
Note 1:
R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
TABLE 20-1:
Name CVRCON CMCON TRISA
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7 CVREN C2OUT -- Bit 6 CVROE C1OUT -- Bit 5 CVRR C2INV TRISA5 Bit 4 CVRSS C1INV -- Bit 3 CVR3 CIS TRISA3 Bit 2 CVR2 CM2 TRISA2 Bit 1 CVR1 CM1 TRISA1 Bit 0 CVR0 CM0 TRISA0 Reset Values on page 49 49 50
Legend: Shaded cells are not used with the comparator voltage reference.
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NOTES:
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21.0 SPECIAL FEATURES OF THE CPU
21.1.1 CONSIDERATIONS FOR CONFIGURING THE PIC18F45J10 FAMILY DEVICES
PIC18F45J10 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * In-Circuit Serial ProgrammingTM (ICSPTM) The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 3.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F45J10 family of devices have a configurable Watchdog Timer which is controlled in software. The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two-Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits.
Unlike most PIC18 microcontrollers, devices of the PIC18F45J10 family do not use persistent memory registers to store configuration information. The configuration bytes are implemented as volatile memory which means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the four words at the top of the on-chip program memory space, known as the Flash Configuration Words. It is stored in program memory in the same order shown in Table 21-1, with CONFIG1L at the lowest address and CONFIG3H at the highest. The data is automatically loaded in the proper Configuration registers during device power-up. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data; this is to make certain that program code is not stored in this address when the code is compiled. The volatile memory cells used for the Configuration bits always reset to `1' on Power-on Resets. For all other type of Reset events, the previously programmed values are maintained and used without reloading from program memory. The four Most Significant bits of CONFIG1H, CONFIG2H and CONFIG3H in program memory should also be `1111'. This makes these Configuration Words appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation. To prevent inadvertent configuration changes during code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires a device Reset.
21.1
Configuration Bits
The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location 300000h. A complete list is shown in Table 21-1. A detailed explanation of the various bit functions is provided in Register 21-1 through Register 21-8.
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TABLE 21-1:
File Name 300000h 300001h 300002h 300003h 300004h 300005h CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H
CONFIGURATION BITS AND DEVICE IDs
Bit 7 DEBUG --
(2)
Bit 6 XINST --
(2)
Bit 5 STVREN --
(2)
Bit 4 -- --
(2)
Bit 3 -- --
(3)
Bit 2 -- CP0 FOSC2 WDTPS2 -- -- REV2 DEV5
Bit 1 -- -- FOSC1 WDTPS1 -- -- REV1 DEV4
Bit 0 WDTEN -- FOSC0 WDTPS0 -- CCP2MX REV0 DEV3
Default/ Unprogrammed Value(1) 111- ---1 1111 01-11-- -111 1111 1111 ---- ---1111 ---1 xxxx xxxx(4) 0001 110x(4)
IESO --(2) -- --(2) DEV2 DEV10
FCMEN --(2) -- --(2) DEV1 DEV9
-- --(2) -- --(2) DEV0 DEV8
-- --(2) -- --(2) REV4 DEV7
-- WDTPS3 -- -- REV3 DEV6
3FFFFEh DEVID1 3FFFFFh DEVID2 Legend: Note 1: 2: 3: 4:
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. This bit should always be maintained as `0'. See Register 21-7 and Register 21-8 for DEVID values. These registers are read-only and cannot be programmed by the user.
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REGISTER 21-1:
R/WO-1 DEBUG bit 7 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared -n = Value when device is unprogrammed bit 7
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1 STVREN U-0 -- U-0 -- U-0 -- U-0 -- R/WO-1 WDTEN bit 0
R/WO-1 XINST
DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled Unimplemented: Read as `0' WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit)
bit 6
bit 5
bit 4-1 bit 0
REGISTER 21-2:
U-0 --(1) bit 7 Legend: R = Readable bit
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0 --(1) U-0 --(1) U-0 --(1) U-0 --(2) R/WO-1 CP0 U-0 -- U-0 -- bit 0
WO = Write Once bit
U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
-n = Value when device is unprogrammed bit 7-4 bit 3 bit 2 Unimplemented: Read as `1'(1) Unimplemented: Read as `0'(2) CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected Unimplemented: Read as `0'
bit 1-0 Note 1: 2:
The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. This bit should always be maintained as `0'.
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REGISTER 21-3:
R/WO-1 IESO bit 7 Legend: R = Readable bit WO = Write Once bit -n = Value when device is unprogrammed bit 7 U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 -- U-0 -- U-0 -- R/WO-1 FOSC2 R/WO-1 FOSC1 R/WO-1 FOSC0 bit 0
R/WO-1 FCMEN
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Unimplemented: Read as `0' FOSC2: Default/Reset System Clock Select bit 1 = Clock selected by FOSC<1:0> as system clock is enabled when OSCCON<1:0> = 00 0 = INTRC enabled as system clock when OSCCON<1:0> = 00 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator, PLL enabled and under software control, CLKO function on OSC2 10 = EC oscillator, CLKO function on OSC2 01 = HS oscillator, PLL enabled and under software control 00 = HS oscillator
bit 6
bit 5-3 bit 2
bit 1-0
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REGISTER 21-4:
U-0 --(1) bit 7 Legend: R = Readable bit WO = Write Once bit -n = Value when device is unprogrammed bit 7-4 bit 3-0 Unimplemented: Read as `1'(1) WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 --(1) U-0 --(1) U-0 --(1) R/WO-1 WDTPS3 R/WO-1 WDTPS2 R/WO-1 WDTPS1 R/WO-1 WDTPS0 bit 0
Note 1:
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REGISTER 21-5:
U-0 -- bit 7 Legend: R = Readable bit WO = Write Once bit -n = Value when device is unprogrammed bit 7-0 Unimplemented: Read as `0' U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
REGISTER 21-6:
U-0 --(1) bit 7 Legend: R = Readable bit
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0 --(1) U-0 --(1) U-0 --(1) U-0 -- U-0 -- U-0 -- R/WO-1 CCP2MX bit 0
WO = Write Once bit
U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
-n = Value when device is unprogrammed bit 7-1 bit 0 Unimplemented: Read as `1'(1) CCP2MX: CCP2 MUX bit 1 = CCP2 is multiplexed with RC1 0 = CCP2 is multiplexed with RB3
Note 1:
The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed.
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REGISTER 21-7:
R DEV2(1) bit 7 Legend: R = Read-only bit -n = Value when device is unprogrammed bit 7-5 DEV<2:0>: Device ID bits 011 = PIC18LF4XJ10 010 = PIC18LF2XJ10 001 = PIC18F4XJ10 000 = PIC18F2XJ10 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. Where values for DEV<2:0> are shared by more than one device number, the specific device is always identified by using the entire DEV<10:0> bit sequence. U = Unimplemented bit, read as `0' u = Unchanged from programmed state
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F45J10 FAMILY DEVICES
R R
(1)
R
(1)
R REV3
R REV2
R REV1
R REV0 bit 0
DEV1
DEV0
REV4
bit 4-0
Note 1:
REGISTER 21-8:
R DEV10(1) bit 7 Legend: R = Read-only bit bit 7-0
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F45J10 FAMILY DEVICES
R R DEV8(1) R DEV7(1) R DEV6(1) R DEV5(1) R DEV4(1) R DEV3(1) bit 0
DEV9(1)
DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0001 1100 = PIC18FX5J10 devices 0001 1101 = PIC18FX4J10 devices The values for DEV<10:3> may be shared with other device families. The specific device is always identified by using the entire DEV<10:0> bit sequence.
Note 1:
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21.2 Watchdog Timer (WDT)
For PIC18F45J10 family devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexor, controlled by the WDTPS bits in Configuration Register 2H. Available periods range from about 4 ms to 135 seconds (2.25 minutes) depending on voltage, temperature and Watchdog postscaler. The WDT and postscaler are cleared whenever a SLEEP or CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has occurred. Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: When a CLRWDT instruction is executed, the postscaler count will be cleared.
21.2.1
CONTROL REGISTER
The WDTCON register (Register 21-9) is a readable and writable register. The SWDTEN bit enables or disables WDT operation.
FIGURE 21-1:
SWDTEN
WDT BLOCK DIAGRAM
Enable WDT INTRC Control /128 Wake-up from Power-Managed Modes Programmable Postscaler 1:1 to 1:32,768 4 Reset WDT Reset
WDT Counter INTRC Oscillator
CLRWDT
All Device Resets WDTPS<3:0> Sleep
WDT
REGISTER 21-9:
u-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off This bit has no effect if the Configuration bit, WDTEN, is enabled.
Note 1:
TABLE 21-2:
Name RCON WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 IPEN -- Bit 6 -- -- Bit 5 CM -- Bit 4 RI -- Bit 3 TO -- Bit 2 PD -- Bit 1 POR -- Bit 0 BOR SWDTEN Reset Values on page 48 48
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer.
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21.3
Note:
On-Chip Voltage Regulator
The on-chip voltage regulator is only available in parts designated with an "F", such as PIC18F45J10.
21.3.1
ON-CHIP REGULATOR AND BOR
In parts designated "LF", the microcontroller core is powered from an external source that is separate from VDD. This voltage is supplied on the VDDCORE pin. In "F" devices, a low-ESR capacitor must be connected to the VDDCORE/VCAP pin for proper device operation. In parts designated with an "LF" part number (i.e., PIC18LF45J10), power to the core must be supplied on VDDCORE/VCAP. It is always good design practice to have sufficient capacitance on all supply pins. Examples are shown in Figure 21-2. Note: In parts designated with an "LF", such as PIC18LF45J10, VDDCORE must never exceed VDD.
When the on-chip regulator is enabled, PIC18F45J10 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a BOR Reset. This event is captured by the BOR flag bit (RCON<0>). The operation of the BOR is described in more detail in Section 5.4 "Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)" and Section 5.4.1 "Detecting BOR". The brown-out voltage levels are specific in Section 23.1 "DC Characteristics: Supply Voltage".
21.3.2
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up requirements for the device. While powering up, VDDCORE must never exceed VDD by 0.3 volts.
The specifications for core voltage and capacitance are listed inTable 24-4 of Section 24.0 "Electrical Characteristics".
FIGURE 21-2:
CONNECTIONS FOR THE ON-CHIP REGULATOR
3.3V PIC18FXXJ10 VDD VDDCORE/VCAP
PIC18FXXJ10 Devices (Regulator Enabled):
CEFC
VSS
PIC18LFXXJ10 Devices (Regulator Disabled): 2.5V PIC18LFXXJ10 VDD VDDCORE/VCAP VSS
OR 2.5V 3.3V PIC18LFXXJ10 VDD VDDCORE/VCAP VSS
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21.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. Two-Speed Start-up should be enabled only if the primary oscillator mode is HS (Crystal-Based) modes. Since the EC mode does not require an OST start-up delay, Two-Speed Start-up should be disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a POR Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
21.4.1
SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 4.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS<1:0> bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode.
FIGURE 21-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC OSC1 TOST(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 OSTS bit Set PC + 4 PC + 6
Wake From Interrupt Event
Note 1:
TOST = 1024 TOSC. These intervals are not shown to scale.
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21.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 21-4) is accomplished by creating a sample clock signal which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF<2:0> immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IRCF<2:0> prior to entering Sleep mode. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible.
21.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTRC clock when a clock failure is detected; this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock Monitor events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out.
FIGURE 21-4:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
Peripheral Clock
S
Q
INTRC Source (32 s)
/ 64 488 Hz (2.048 ms)
C
Q
21.5.2
EXITING FAIL-SAFE OPERATION
Clock Failure Detected
Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 21-5). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * the device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition); and * the WDT is reset. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 4.1.4 "Multiple Sleep Commands" and Section 21.4.1 "Special Considerations for Using Two-Speed Start-up" for more details.
The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 2H (with the OST oscillator, start-up delays if running in HS mode). The INTRC oscillator provides the device clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTRC oscillator. The OSCCON register will remain in its Reset state until a power-managed mode is entered.
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FIGURE 21-5:
Sample Clock Device Clock Output CM Output (Q) OSCFIF Failure Detected Oscillator Failure
FSCM TIMING DIAGRAM
CM Test Note:
CM Test
CM Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
21.5.3
FSCM INTERRUPTS IN POWER-MANAGED MODES
21.5.4
POR OR WAKE-UP FROM SLEEP
By entering a power-managed mode, the clock multiplexor selects the clock source selected by the OSCCON register. Fail-Safe Monitoring of the power-managed clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexor. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source.
The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is either EC or INTRC modes, monitoring can begin immediately following these events. For HS mode, the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FSCM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST timer has timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged.
As noted in Section 21.4.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled.
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21.6 Program Verification and Code Protection 21.7 In-Circuit Serial Programming
PIC18F45J10 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
For all devices in the PIC18F45J10 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode.
21.6.1
CONFIGURATION REGISTER PROTECTION
The Configuration registers are protected against untoward changes or reads in two ways. The primary protection is the write-once feature of the Configuration bits which prevents reconfiguration once the bit has been programmed during a power cycle. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell-level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the CP0 bit is set, the source data for device configuration is also protected as a consequence.
21.8
In-Circuit Debugger
When the DEBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 21-3 shows which resources are required by the background debugger.
TABLE 21-3:
I/O pins: Stack:
DEBUGGER RESOURCES
RB6, RB7 2 levels 512 bytes 32 bytes
Program Memory: Data Memory:
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NOTES:
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22.0 INSTRUCTION SET SUMMARY
PIC18F45J10 family devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 22-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 22-2, lists the standard instructions recognized by the Microchip Assembler (MPASMTM). Section 22.1.1 "Standard Instruction Set" provides a description of each instruction.
22.1
Standard Instruction Set
The standard PIC18 instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations
The PIC18 instruction set summary in Table 22-2 lists byte-oriented, bit-oriented, literal and control operations. Table 22-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a')
The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a')
The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located.
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TABLE 22-1:
Field a
OPCODE FIELD DESCRIPTIONS
Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. Destination select bit d = 0: store result in WREG d = 1: store result in file register f Destination: either the WREG register or the specified register file location. 8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). 12-bit register file address (000h to FFFh). This is the source address. 12-bit register file address (000h to FFFh). This is the destination address. Global Interrupt Enable bit. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: No change to register (such as TBLPTR with table reads and writes) Post-Increment register (such as TBLPTR with table reads and writes) Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Power-down bit. Product of Multiply High Byte. Product of Multiply Low Byte. Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) 21-bit Table Pointer (points to a program memory location). 8-bit Table Latch. Time-out bit. Top-of-Stack. Unused or unchanged. Watchdog Timer. Working register (accumulator). Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination).
bbb BSR C, DC, Z, OV, N d
dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s
TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr] <> italics
Optional argument. Indicates an indexed address. The contents of text. Specifies bit n of the register indicated by the pointer expr. Assigned to. Register bit field. In the set of. User-defined term (font is Courier New).
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FIGURE 22-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 15 10 OPCODE d 9 87 a f (FILE #) 0 ADDWF MYREG, W, B Example Instruction
d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 f (Destination FILE #) 0 f (Source FILE #) 0 MOVFF MYREG1, MYREG2
f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B OPCODE b (BIT #) a
b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 GOTO Label 8 7 k (literal) 0 MOVLW 7Fh
n = 20-bit immediate value 15 OPCODE 15 1111 S = Fast bit 15 OPCODE 15 OPCODE 87 n<7:0> (literal) 11 10 n<10:0> (literal) 0 BC MYFUNC 0 BRA MYFUNC 12 11 n<19:8> (literal) 87 S n<7:0> (literal) 0 0 CALL MYFUNC
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TABLE 22-2:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF Note 1: f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st Word fd (destination) 2nd Word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f, Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
1, 2 1, 2
1, 2
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N
1, 2
4 1, 2
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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TABLE 22-2:
Mnemonic, Operands BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP Note 1: f, b, a f, b, a f, b, a f, b, a f, d, a n n n n n n n n n n, s -- -- n -- -- -- -- n s k s -- Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st Word 2nd Word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st Word 2nd Word No Operation No Operation Pop Top of Return Stack (TOS) Push Top of Return Stack (TOS) Relative Call Software Device Reset Return from Interrupt Enable Return with Literal in WREG Return from Subroutine Go into Standby mode 1 1 1 (2 or 3) 1 (2 or 3) 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None None None None None None None None None None None TO, PD C None 1, 2 1, 2 3, 4 3, 4 1, 2
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
CONTROL OPERATIONS 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
4
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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TABLE 22-2:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: k k k f, k k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd Word to FSR(f) 1st Word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG Table Read Table Read with Post-Increment Table Read with Post-Decrement Table Read with Pre-Increment Table Write Table Write with Post-Increment Table Write with Post-Decrement Table Write with Pre-Increment 1 1 1 2 1 1 1 2 1 1 2 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
DATA MEMORY PROGRAM MEMORY OPERATIONS 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111
2
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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22.1.1
ADDLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
STANDARD INSTRUCTION SET
ADD Literal to W
ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z 0000 1111 kkkk kkkk The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1 Q1 Q2 Read literal `k' Q3 Process Data Q4 Write to W Operation: Status Affected: Encoding: Description: k
ADDWF
Syntax: Operands:
ADD W to f
ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z 0010 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}}
Words: Cycles: Q Cycle Activity: Decode
Example:
ADDLW
15h
Before Instruction W = 10h After Instruction W = 25h Words: Cycles:
Q Cycle Activity: Q1 Decode Q2 Read register `f' ADDWF 17h 0C2h 0D9h 0C2h Q3 Process Data REG, 0, 0 Q4 Write to destination
Example: W = REG = After Instruction W REG = =
Before Instruction
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
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ADDWFC
Syntax: Operands:
ADD W and Carry bit to f
ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N,OV, C, DC, Z 0010 00da ffff ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}}
ANDLW
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
AND Literal with W
ANDLW 0 k 255 (W) .AND. k W N, Z 0000 1011 kkkk kkkk The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2 Read literal `k' ANDLW A3h 03h Q3 Process Data 05Fh Q4 Write to W k
Operation: Status Affected: Encoding: Description:
Example: W = After Instruction W =
Before Instruction
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' ADDWFC 1 02h 4Dh 0 02h 50h
Q3 Process Data REG, 0, 1
Q4 Write to destination
Example:
Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W =
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ANDWF
Syntax: Operands:
AND W with f
ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z 0001 01da ffff ffff The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' ANDWF 17h C2h 02h C2h Q3 Process Data REG, 0, 0 Q4 Write to destination f {,d {,a}}
BC
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Carry
BC n -128 n 127 if Carry bit is `1', (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn If the Carry bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BC 5
Q4 Write to PC No operation Q4 No operation
Words: Cycles: Q Cycle Activity: Decode
Example: W = REG = After Instruction W REG = =
Before Instruction
Example:
Before Instruction PC After Instruction If Carry PC If Carry PC
address (HERE) 1; address (HERE + 12) 0; address (HERE + 2)
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BCF
Syntax: Operands:
Bit Clear f
BCF f, b {,a} 0 f 255 0b7 a [0,1] 0 f None 1001 bbba ffff ffff Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' BCF Q3 Process Data FLAG_REG, C7h 47h Q4 Write register `f' 7, 0
BN
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Negative
BN n -128 n 127 if Negative bit is `1', (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1
Words: Cycles: Q Cycle Activity:
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BN Jump
Q4 Write to PC No operation Q4 No operation
Example:
Decode
Before Instruction FLAG_REG = After Instruction FLAG_REG =
Example:
Before Instruction PC After Instruction If Negative PC If Negative PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
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BNC
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Carry
BNC n -128 n 127 if Carry bit is `0', (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn If the Carry bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
BNN
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Negative
BNN n -128 n 127 if Negative bit is `0', (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn If the Negative bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNC Jump Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BNN Jump
Q4 Write to PC No operation Q4 No operation
Read literal `n' No operation
Read literal `n' HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If Carry PC If Carry PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
Before Instruction PC After Instruction If Negative PC If Negative PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
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BNOV
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Overflow
BNOV n -128 n 127 if Overflow bit is `0', (PC) + 2 + 2n PC None 1110 0101 nnnn nnnn If the Overflow bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
BNZ
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Zero
BNZ n -128 n 127 if Zero bit is `0', (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn If the Zero bit is `0', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BNZ Jump
Q4 Write to PC No operation Q4 No operation
Read literal `n' No operation
Read literal `n' HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If Overflow PC If Overflow PC
Before Instruction PC After Instruction If Zero PC If Zero PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
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BRA
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Unconditional Branch
BRA n -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn Add the 2's complement number, `2n', to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q1 Decode No operation Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC No operation
BSF
Syntax: Operands:
Bit Set f
BSF f, b {,a} 0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' BSF = = Q3 Process Data Q4 Write register `f'
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity:
Example:
HERE = =
BRA
Jump
Before Instruction PC After Instruction PC
address (HERE) address (Jump)
Example:
FLAG_REG, 7, 1 0Ah 8Ah
Before Instruction FLAG_REG After Instruction FLAG_REG
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BTFSC
Syntax: Operands:
Bit Test File, Skip if Clear
BTFSC f, b {,a} 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Decode Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q3 Process Data Q3 No operation Q3 No operation No operation BTFSC : : Q4 No operation
BTFSS
Syntax: Operands:
Bit Test File, Skip if Set
BTFSS f, b {,a} 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation BTFSS : : Q4 No operation Q4 No operation Q4 No operation No operation
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Words: Cycles:
Words: Cycles:
Q Cycle Activity:
Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = =
If skip: Q1 No operation Q1 No operation No operation Example: Q4 No operation Q4 No operation No operation
Q1 No operation Q1 No operation No operation Example:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
FLAG, 1, 0
FLAG, 1, 0
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (FALSE) 1; address (TRUE)
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BTG
Syntax: Operands:
Bit Toggle f
BTG f, b {,a} 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' BTG Q3 Process Data PORTC, 4, 0 Q4 Write register `f'
BOV
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Overflow
BOV n -128 n 127 if Overflow bit is `1', (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity:
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BOV Jump
Q4 Write to PC No operation Q4 No operation
Example:
Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h]
Example:
Before Instruction PC After Instruction If Overflow PC If Overflow PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
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BZ
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Zero
BZ n -128 n 127 if Zero bit is `1', (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number, `2n', is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
CALL
Syntax: Operands: Operation:
Subroutine Call
CALL k {,s} 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BZ Jump
Q4 Write to PC No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode
Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Q3 Q4 Read literal `k'<19:8>, Write to PC No operation
Read literal PUSH PC to `k'<7:0>, stack No operation HERE No operation CALL
Example:
Before Instruction PC After Instruction If Zero PC If Zero PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
No operation Example:
THERE, 1
Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS =
address (HERE) address (THERE) address (HERE + 4) W BSR STATUS
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CLRF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Clear f
CLRF f {,a} 0 f 255 a [0,1] 000h f, 1Z Z 0110 101a ffff ffff
CLRWDT
Syntax: Operands: Operation:
Clear Watchdog Timer
CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. 1 1
Status Affected: Encoding: Description:
Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 No operation CLRWDT = = = = = ?
Q3 Process Data
Q4 No operation
Words: Cycles: Q Cycle Activity: Q1 Decode
Example: Q2 Q3 Process Data FLAG_REG, 1 5Ah 00h Q4 Write register `f'
Read register `f' CLRF = =
Example:
Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD
00h 0 1 1
Before Instruction FLAG_REG After Instruction FLAG_REG
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COMF
Syntax: Operands:
Complement f
COMF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest N, Z 0001 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
CPFSEQ
Syntax: Operands: Operation:
Compare f with W, Skip if f = W
CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation f {,a}
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Q1 Decode
Words: Q2 Read register `f' COMF 13h If skip: 13h ECh Q3 Process Data REG, 0, 0 Q4 Write to destination Cycles:
Q Cycle Activity: Example: Before Instruction REG = After Instruction REG = W = Decode
Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL = = = = = =
CPFSEQ REG, 0 : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Before Instruction PC Address W REG After Instruction If REG PC If REG PC
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CPFSGT
Syntax: Operands: Operation:
Compare f with W, Skip if f > W
CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. f {,a}
CPFSLT
Syntax: Operands: Operation:
Compare f with W, Skip if f < W
CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation Q4 No operation Q4 No operation Q4 No operation No operation f {,a}
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 Q2 No operation Q2 No operation No operation HERE NLESS LESS = = < = = No operation Q1 Q2 Read register `f'
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NGREATER GREATER = = > = = Q4 No operation Q4 No operation No operation Q2 Read register `f' Q3 Process Data Q4 No operation
If skip and followed by 2-word instruction: No operation No operation Example:
CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
CPFSGT REG, 0 : :
Before Instruction PC W After Instruction If REG PC If REG PC
Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
Before Instruction PC W After Instruction If REG PC If REG PC
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DAW
Syntax: Operands: Operation:
Decimal Adjust W Register
DAW None If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 W<3:0>; else, (W<3:0>) W<3:0> If [W<7:4> + DC > 9] or [C = 1] then, (W<7:4>) + 6 + DC W<7:4>; else, (W<7:4>) + DC W<7:4>
DECF
Syntax: Operands:
Decrement f
DECF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z 0000 01da ffff ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' DECF 01h 0 00h 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
C 0000 0000 0000 0111 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Words: Q2 Read register W DAW Q3 Process Data Q4 Write W Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1:
Before Instruction W = C = DC = After Instruction W C DC Example 2: = = = A5h 0 0 05h 1 0 Example:
Before Instruction CNT = Z = After Instruction CNT = Z =
Before Instruction W = C = DC = After Instruction W C DC = = = CEh 0 0 34h 1 0
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DECFSZ
Syntax: Operands:
Decrement f, Skip if 0
DECFSZ f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE CONTINUE Q3 Process Data Q3 No operation Q3 No operation No operation DECFSZ GOTO Q4 Write to destination Q4 No operation Q4 No operation No operation CNT, 1, 1 LOOP
DCFSNZ
Syntax: Operands:
Decrement f, Skip if Not 0
DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation DCFSNZ : : = = = = = ? TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) Q4 Write to destination Q4 No operation Q4 No operation No operation f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 Q2 Decode If skip: Q1 No operation Q1 No operation No operation Example:
Read register `f'
If skip and followed by 2-word instruction:
No operation Q2 No operation No operation HERE ZERO NZERO
If skip and followed by 2-word instruction:
TEMP, 1, 0
Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC =
Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2)
Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC
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GOTO
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Unconditional Branch
GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8
INCF
Syntax: Operands:
Increment f
INCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z 0010 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' INCF FFh 0 ? ? 00h 1 1 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal `k'<7:0>, No operation GOTO THERE
Q3 No operation No operation
Q4 Read literal `k'<19:8>, Write to PC No operation Words: Cycles: Q Cycle Activity:
No operation Example:
After Instruction PC = Address (THERE)
Example:
Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC =
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INCFSZ
Syntax: Operands:
Increment f, Skip if 0
INCFSZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE NZERO ZERO Q3 Process Data Q3 No operation Q3 No operation No operation INCFSZ : : Q4 Write to destination f {,d {,a}}
INFSNZ
Syntax: Operands:
Increment f, Skip if Not 0
INFSNZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation INFSNZ Q4 Write to destination Q4 No operation Q4 No operation No operation f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Decode If skip: Q1 No operation Q1 No operation No operation Example: Q4 No operation Q4 No operation No operation
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO Q2 Read register `f'
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
CNT, 1, 0
REG, 1, 0
Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC =
Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction PC = After Instruction REG = If REG PC = If REG = PC =
Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
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IORLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W
IORLW k 0 k 255 (W) .OR. k W N, Z 0000 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. 1 1 Q1 Q2 Read literal `k' IORLW 9Ah BFh Q3 Process Data 35h Q4 Write to W
IORWF
Syntax: Operands:
Inclusive OR W with f
IORWF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z 0001 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' IORWF 13h 91h 13h 93h Q3 Process Data RESULT, 0, 1 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Example: W = After Instruction W =
Before Instruction Words: Cycles: Q Cycle Activity: Decode
Example:
Before Instruction RESULT = W = After Instruction RESULT = W =
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LFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MSB Q3 Process Data Q4 Write literal `k' MSB to FSRfH Write literal `k' to FSRfL
Load FSR
LFSR f, k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk
MOVF
Syntax: Operands:
Move f
MOVF f {,d {,a}} 0 f 255 d [0,1] a [0,1] f dest N, Z 0101 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' MOVF = = = = Q3 Process Data REG, 0, 0 22h FFh 22h 22h Q4 Write W
Operation: Status Affected: Encoding: Description:
The 12-bit literal `k' is loaded into the File Select Register pointed to by `f'. 2 2
Decode
Read literal `k' LSB
Process Data
Example: After Instruction FSR2H FSR2L
LFSR 2, 3ABh = = 03h ABh Words: Cycles: Q Cycle Activity:
Example:
Before Instruction REG W After Instruction REG W
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MOVFF
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description:
Move f to f
MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd
MOVLB
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to Low Nibble in BSR
MOVLW k 0 k 255 k BSR None 0000 0001 kkkk kkkk The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0', regardless of the value of k7:k4. 1 1 Q1 Q2 Read literal `k' MOVLB 02h 05h Q3 Process Data 5 Q4 Write literal `k' to BSR
The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. 2 2 (3)
Words: Cycles: Q Cycle Activity: Decode
Example:
Before Instruction BSR Register = After Instruction BSR Register =
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' (src) No operation No dummy read
Q3 Process Data No operation
Q4 No operation Write register `f' (dest)
Decode
Example:
MOVFF = = = =
REG1, REG2 33h 11h 33h 33h
Before Instruction REG1 REG2 After Instruction REG1 REG2
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MOVLW
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MOVLW W = 5Ah Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' MOVWF 4Fh FFh 4Fh 4Fh Q3 Process Data REG, 0 Q4 Write register `f' Q3 Process Data 5Ah Q4 Write to W 1 1
Move Literal to W
MOVLW k 0 k 255 kW None 0000 1110 kkkk kkkk The eight-bit literal `k' is loaded into W.
MOVWF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move W to f
MOVWF 0 f 255 a [0,1] (W) f None 0110 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,a}
Example: After Instruction
Example: W = REG = After Instruction W REG = =
Before Instruction
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MULLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply Literal with W
MULLW k 0 k 255 (W) x k PRODH:PRODL None 0000 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. 1 1 Q1 Q2 Read literal `k' Q3 Process Data Q4 Write registers PRODH: PRODL
MULWF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply W with f
MULWF 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' Q3 Process Data Q4 Write registers PRODH: PRODL f {,a}
Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction W PRODH PRODL After Instruction W PRODH PRODL
MULLW = = = = = =
0C4h E2h ? ? E2h ADh 08h Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL
MULWF = = = = = = = =
REG, 1 C4h B5h ? ? C4h B5h 8Ah 94h
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NEGF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Negate f
NEGF f {,a} 0 f 255 a [0,1] (f)+1f N, OV, C, DC, Z 0110 110a ffff ffff Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' NEGF Q3 Process Data REG, 1 Q4 Write register `f'
NOP
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
No Operation
NOP None No operation None 0000 1111 1 1 Q2 No operation Q3 No operation Q4 No operation 0000 xxxx 0000 xxxx 0000 xxxx
No operation.
Example: None.
Words: Cycles: Q Cycle Activity:
Example:
Before Instruction REG = After Instruction REG =
0011 1010 [3Ah] 1100 0110 [C6h]
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POP
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Pop Top of Return Stack
POP None (TOS) bit bucket None 0000 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q1 Decode Q2 No operation POP GOTO Q3 POP TOS value Q4 No operation
PUSH
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Push Top of Return Stack
PUSH None (PC + 2) TOS None 0000 0000 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1 Q1 Decode Q2 PUSH PC + 2 onto return stack PUSH = = = = = 345Ah 0124h 0126h 0126h 345Ah Q3 No operation Q4 No operation
Words: Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity:
Example:
Example: NEW = = = = 0031A2h 014332h 014332h NEW
Before Instruction TOS Stack (1 level down) After Instruction TOS PC
Before Instruction TOS PC After Instruction PC TOS Stack (1 level down)
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RCALL
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Relative Call
RCALL n -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number, `2n', to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q1 Q2 Read literal `n' PUSH PC to stack Q3 Process Data Q4 Write to PC
RESET
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Reset
RESET None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2 Start Reset RESET Reset Value Reset Value Q3 No operation Q4 No operation
Words: Cycles: Q Cycle Activity: Decode
Example: After Instruction Registers = Flags* =
No operation Example:
No operation HERE
No operation RCALL Jump
No operation
Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2)
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RETFIE
Syntax: Operands: Operation:
Return from Interrupt
RETFIE {s} s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged GIE/GIEH, PEIE/GIEL. 0000 0000 0001 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2
RETLW
Syntax: Operands: Operation:
Return Literal to W
RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q1 Q2 Read literal `k' No operation Q3 Process Data No operation Q4 POP PC from stack, Write to W No operation
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Words: Cycles: Q Cycle Activity: Q1 Decode
No operation Example: Q2 Q3 No operation Q4 POP PC from stack Set GIEH or GIEL
No operation
No operation Example:
No operation RETFIE 1
No operation
No operation
After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W =
W contains table offset value W now has table value
W = offset Begin table
End of table
07h value of kn
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RETURN
Syntax: Operands: Operation:
Return from Subroutine
RETURN {s} s [0,1] (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q1 Q2 No operation No operation Q3 Process Data No operation Q4 POP PC from stack No operation
RLCF
Syntax: Operands:
Rotate Left f through Carry
RLCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) C, (C) dest<0> C, N, Z 0011 01da ffff ffff The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f
Operation:
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode No operation
Words: Cycles: Q Cycle Activity:
1 1 Q1 Decode Q2 Read register `f' RLCF Q3 Process Data Q4 Write to destination
Example:
RETURN
After Instruction: PC = TOS
Example: Before Instruction REG = C = After Instruction REG = W = C =
REG, 0, 0
1110 0110 0 1110 0110 1100 1100 1
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RLNCF
Syntax: Operands:
Rotate Left f (No Carry)
RLNCF 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) dest<0> N, Z 0100 01da ffff ffff f {,d {,a}}
RRCF
Syntax: Operands:
Rotate Right f through Carry
RRCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) C, (C) dest<7> C, N, Z 0011 00da ffff ffff The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f
Operation: Status Affected: Encoding: Description:
Operation:
Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f
Words: Cycles: Q Cycle Activity: Q1 Decode
1 1 Q2 Read register `f' RLNCF Q3 Process Data Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode Q2 1 1
Q3 Process Data REG, 0, 0
Q4 Write to destination
Example: Before Instruction REG = After Instruction REG =
REG, 1, 0 Example:
Read register `f' RRCF
1010 1011 0101 0111
Before Instruction REG = C = After Instruction REG = W = C =
1110 0110 0 1110 0110 0111 0011 0
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RRNCF
Syntax: Operands:
Rotate Right f (No Carry)
RRNCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) dest<7> N, Z 0100 00da ffff ffff The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f
SETF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Set f
SETF f {,a} 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' SETF = = 5Ah FFh Q3 Process Data REG, 1 Q4 Write register `f'
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity: Q1 Decode
1 1 Q2 Read register `f' RRNCF Q3 Process Data REG, 1, 0 Q4 Write to destination Example:
Before Instruction REG After Instruction REG
Example 1:
Before Instruction REG = After Instruction REG = Example 2:
1101 0111 1110 1011 REG, 0, 0
RRNCF
Before Instruction W = REG = After Instruction W = REG =
? 1101 0111 1110 1011 1101 0111
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SLEEP
Syntax: Operands: Operation:
Enter Sleep mode
SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 1 1 Q1 Q2 No operation SLEEP Q3 Process Data Q4 Go to Sleep
SUBFWB
Syntax: Operands:
Subtract f from W with Borrow
SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z 0101 01da ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction TO = ? ? PD =
Words: Cycles: Q Cycle Activity: Q1 Decode
After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared.
Q2 Read register `f'
Q3 Process Data
Q4 Write to destination
SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative SUBFWB REG, 0, 0 Example 2: Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0
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SUBLW
Syntax: Operands: Operation: Status Affected: Encoding: Description Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = Q2 Read literal `k' SUBLW 01h ? 01h 1 ; result is positive 0 0 SUBLW 02h ? 00h 1 ; result is zero 1 0 SUBLW 03h ? FFh ; (2's complement) 0 ; result is negative 0 1 02h 02h Q3 Process Data 02h Q4 Write to W
Subtract W from Literal
SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z 0000 1000 kkkk kkkk W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1
SUBWF
Syntax: Operands:
Subtract W from f
SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z 0101 11da ffff ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' SUBWF 3 2 ? 1 2 1 0 0 SUBWF 2 2 ? 2 0 1 1 0 SUBWF 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1 Q3 Process Data REG, 1, 0 Q4 Write to destination f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N =
; result is positive
REG, 0, 0
; result is zero
REG, 1, 0
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SUBWFB
Syntax: Operands:
Subtract W from f with Borrow
SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z 0101 10da ffff ffff f {,d {,a}}
SWAPF
Syntax: Operands:
Swap f
SWAPF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' SWAPF 53h 35h Q3 Process Data REG, 1, 0 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1:
Words: Cycles: Q3 Process Data REG, 1, 0 (0001 1001) (0000 1101) (0000 1011) (0000 1101) ; result is positive Example: Q4 Write to destination Q Cycle Activity: Decode
Q2 Read register `f' SUBWFB 19h 0Dh 1 0Ch 0Dh 1 0 0
Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W C Z N = = = =
Before Instruction REG = After Instruction REG =
SUBWFB REG, 0, 0 1Bh 1Ah 0 1Bh 00h 1 1 0 SUBWFB 03h 0Eh 1 F5h 0Eh 0 0 1 (0001 1011) (0001 1010)
(0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1101)
(1111 0100) ; [2's comp] (0000 1101) ; result is negative
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TBLRD
Syntax: Operands: Operation:
Table Read
TBLRD ( *; *+; *-; +*) None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT
TBLRD
Example 1:
Table Read (Continued)
TBLRD *+ ; = = = = = 55h 00A356h 34h 34h 00A357h
Before Instruction TABLAT TBLPTR MEMORY (00A356h) After Instruction TABLAT TBLPTR Example 2: TBLRD Before Instruction TABLAT TBLPTR MEMORY (01A357h) MEMORY (01A358h) After Instruction TABLAT TBLPTR
+* ; = = = = = = AAh 01A357h 12h 34h 34h 01A358h
Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2
Words: Cycles: Q1 Decode No operation
Q Cycle Activity: Q2 No operation No operation (Read Program Memory) Q3 No operation No operation Q4 No operation No operation (Write TABLAT)
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TBLWT
Syntax: Operands: Operation:
Table Write
TBLWT ( *; *+; *-; +*) None if TBLWT *, (TABLAT) Holding Register, TBLPTR - No Change; if TBLWT *+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT *-, (TABLAT) Holding Register, (TBLPTR) - 1 TBLPTR; if TBLWT +*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +*
TBLWT
Example 1:
Table Write (Continued)
TBLWT *+;
Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h
Status Affected: Encoding:
Description:
This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 7.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q1 Decode Q2 Q3 Q4
Words: Cycles: Q Cycle Activity:
No No No operation operation operation
No No No No operation operation operation operation (Write to (Read Holding TABLAT) Register )
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TSTFSZ
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Test f, Skip if 0
TSTFSZ f {,a} 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE NZERO ZERO = = = = Q3 Process Data Q3 No operation Q3 No operation No operation TSTFSZ : : Q4 No operation Q4 No operation Q4 No operation No operation
XORLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR Literal with W
XORLW k 0 k 255 (W) .XOR. k W N, Z 0000 1010 kkkk kkkk The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. 1 1 Q1 Q2 Read literal `k' XORLW B5h 1Ah Q3 Process Data 0AFh Q4 Write to W
Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction W = After Instruction W =
Words: Cycles:
Q Cycle Activity: Decode If skip: Q1 No operation Q1 No operation No operation Example:
If skip and followed by 2-word instruction:
CNT, 1
Before Instruction PC After Instruction If CNT PC If CNT PC
Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO)
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XORWF
Syntax: Operands:
Exclusive OR W with f
XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z 0001 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' XORWF AFh B5h 1Ah B5h Q3 Process Data REG, 1, 0 Q4 Write to destination f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Example:
Before Instruction REG = W = After Instruction REG = W =
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22.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F45J10 family devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: * dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 22-3. Detailed descriptions are provided in Section 22.2.2 "Extended Instruction Set". The opcode field descriptions in Table 22-1 (page 250) apply to both the standard and extended PIC18 instruction sets. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler.
22.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 22.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }").
TABLE 22-3:
Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k
EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word Description Add Literal to FSR Add Literal to FSR2 and Return Call Subroutine using WREG Move zs (source) to 1st Word 2nd Word fd (destination) Move zs (source) to 1st Word 2nd Word zd (destination) Store Literal at FSR2, Decrement FSR2 Subtract Literal from FSR Subtract Literal from FSR2 and Return Cycles MSb 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk LSb kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk Status Affected None None None None None None None None
zs, fd zs, zd k f, k k
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22.2.2
ADDFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' Q3 Process Data Q4 Write to FSR
EXTENDED INSTRUCTION SET
Add Literal to FSR
ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk kkkk The 6-bit literal `k' is added to the contents of the FSR specified by `f'. 1 1 Status Affected: Encoding: Description:
ADDULNK
Syntax: Operands: Operation:
Add Literal to FSR2 and Return
ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2
Example:
ADDFSR 2, 23h 03FFh 0422h
Words: Cycles: Q Cycle Activity: Q1 Decode No Operation
Before Instruction FSR2 = After Instruction FSR2 =
Q2 Read literal `k' No Operation
Q3 Process Data No Operation
Q4 Write to FSR No Operation
Example:
ADDULNK 23h 03FFh 0100h 0422h (TOS)
Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
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CALLW
Syntax: Operands: Operation:
Subroutine Call Using WREG
CALLW None (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU None 0000 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR. 1 2 Q1 Q2 Read WREG No operation Q3 PUSH PC to stack No operation Q4 No operation No operation
MOVSF
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description:
Move Indexed to f
MOVSF [zs], fd 0 zs 127 0 fd 4095 ((FSR2) + zs) fd None 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd
Status Affected: Encoding: Description
Words: Cycles: Q Cycle Activity: Decode No operation
The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs' in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. 2 2
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2
Q3
Q4 Read source reg Write register `f' (dest)
Example:
HERE
CALLW Decode
Determine Determine source addr source addr No operation No dummy read No operation
Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W =
address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h Example:
MOVSF = = = = = =
[05h], REG2 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2
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MOVSS
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (dest.) Description
Move Indexed to Indexed
MOVSS [zs], [zd] 0 zs 127 0 zd 127 ((FSR2) + zs) ((FSR2) + zd) None 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd
PUSHL
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Store Literal at FSR2, Decrement FSR2
PUSHL k 0 k 255 k (FSR2), FSR2 - 1 FSR2 None 1111 1010 kkkk kkkk The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. 1 1 Q1 Q2 Read `k' Q3 Process data Q4 Write to destination
The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. 2 2
Words: Cycles: Q Cycle Activity: Decode
Example:
PUSHL 08h = = = = 01ECh 00h 01EBh 08h
Before Instruction FSR2H:FSR2L Memory (01ECh) After Instruction FSR2H:FSR2L Memory (01ECh)
Words: Cycles: Q Cycle Activity: Q1 Decode Decode
Q2
Q3
Q4 Read source reg Write to dest reg
Determine Determine source addr source addr Determine dest addr Determine dest addr
Example:
MOVSS [05h], [06h] = = = = = = 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h
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SUBFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract Literal from FSR
SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) - k FSRf None 1110 1001 ffkk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. 1 1 Q1 Q2 Read register `f' Q3 Process Data Q4 Write to destination
SUBULNK
Syntax: Operands: Operation:
Subtract Literal from FSR2 and Return
SUBULNK k 0 k 63 FSR2 - k FSR2 (TOS) PC
Status Affected: None Encoding: Description: 1110 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 Q1 Decode No Operation Q2 Read register `f' No Operation Q3 Process Data No Operation Q4 Write to destination No Operation
Words: Cycles: Q Cycle Activity: Decode
Words: Cycles:
Example: Before Instruction FSR2 = After Instruction FSR2 =
SUBFSR 2, 23h 03FFh 03DCh
Q Cycle Activity:
Example: Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
SUBULNK 23h 03FFh 0100h 03DCh (TOS)
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22.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely.
22.2.3.1
Extended Instruction Syntax with Standard PIC18 Commands
Note:
In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 6.5.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (`a' = 0), or in a GPR bank designated by the BSR (`a' = 1). When the extended instruction set is enabled and `a' = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 22.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types.
When the extended instruction set is enabled, the file register argument, `f', in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument, `d', functions as before. Refer to the MPLAB(R) IDE, MPASMTM or MPLAB C18 documentation for information on enabling Extended Instruction set support
22.2.4
CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F45J10 family, it is very important to consider the type of code. A large, re-entrant application that is written in `C' and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.
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ADDWF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
ADD W to Indexed (Indexed Literal Offset mode)
ADDWF 0 k 95 d [0,1] (W) + ((FSR2) + k) dest N, OV, C, DC, Z 0010 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). 1 1 Q1 Q2 Read `k' Q3 Process Data [OFST] , 0 = = = = = = 17h 2Ch 0A00h 20h 37h 20h Q4 Write to destination [k] {,d}
BSF
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Bit Set Indexed (Indexed Literal Offset mode)
BSF [k], b 0 f 95 0b7 1 ((FSR2) + k) None 1000 bbb0 kkkk kkkk Bit `b' of the register indicated by FSR2, offset by the value `k', is set. 1 1 Q2 Read register `f' BSF = = = = Q3 Process Data Q4 Write to destination
Words: Cycles: Q Cycle Activity:
Example:
[FLAG_OFST], 7 0Ah 0A00h 55h D5h
Decode
Example: W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch
ADDWF
Before Instruction
Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah
SETF
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Set Indexed (Indexed Literal Offset mode)
SETF [k] 0 k 95 FFh ((FSR2) + k) None 0110 1000 kkkk kkkk The contents of the register indicated by FSR2, offset by `k', are set to FFh. 1 1 Q2 Read `k' Q3 Process Data [OFST] 2Ch 0A00h 00h FFh Q4 Write register
Example:
SETF = = = =
Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch
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22.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS
The latest versions of Microchip's software tools have been designed to fully support the extended instruction set of the PIC18F45J10 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.
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23.0 DEVELOPMENT SUPPORT
23.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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23.2 MPASM Assembler 23.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
23.6 23.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
23.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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23.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 23.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
23.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
23.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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23.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
23.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
23.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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24.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................-40C to +100C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any digital-only input MCLR I/O pin with respect to VSS ........................................................... -0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS ............................................ -0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Maximum output current sunk by any PORTB and PORTC I/O pin........................................................................25 mA Maximum output current sunk by any PORTA, PORTD, and PORTE I/O pin...........................................................4 mA Maximum output current sourced by any PORTB and PORTC I/O pin ..................................................................25 mA Maximum output current sourced by any PORTA, PORTD, and PORTE I/O pin .....................................................4 mA Maximum current sunk by all ports combined.......................................................................................................200 mA Maximum current sourced by all ports combined..................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL)
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 24-1: PIC18LF45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.00V 2.75V Voltage (VDDCORE)(1) 2.50V 2.25V 2.00V PIC18LF24J10/25J10/44J10/45J10 2.35V 2.7V
4 MHz Frequency
40 MHz
For VDDCORE values, 2V to 2.35V, FMAX = (102.85 MHz/V) * (VDDCORE - 2V) + 4 MHz Note 1: For devices without the voltage regulator, VDD and VDDCORE must be maintained so that VDDCORE VDD 3.6V.
FIGURE 24-2:
PIC18F45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
4.0V 3.5V 3.6V PIC18F2XJ10/4XJ10 2.7V
Voltage (VDD)
3.0V 2.5V
4 MHz
40 MHz
Frequency
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D005
24.1
DC Characteristics:
Supply Voltage PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial
PIC18F45J10 Family (Industrial) Param No. D001 D001 D001B Symbol VDD VDD Characteristic Supply Voltage Supply Voltage
Min VDDCORE 2.7
(1)
Typ -- -- --
Max Units 3.6 3.6 2.7 V V V
Conditions PIC18LF4XJ10, PIC18LF2XJ10 PIC18F4X/2XJ10 Valid only in parts designated "LF". See Section 21.3 "On-Chip Voltage Regulator" for details.
VDDCORE External Supply for Microcontroller Core VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset (BOR) Voltage
2.0
D002 D003
1.5 --
-- --
-- 0.15
V V SeeSection 5.3 "Power-on Reset (POR)" for details
D004
SVDD
0.05
--
--
V/ms See Section 5.3 "Power-on Reset (POR)" for details V
D005 Note 1:
VBOR
2.35
2.5
2.7
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Power-Down Current (IPD)(1) All devices 19 25 40 All devices 20 25 45 Note 1: 104 104 184 203 203 289 A A A A A A -40C +25C +85C -40C +25C +85C VDD = 2.5V (Sleep mode) Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No.
VDD = 3.3V (Sleep mode)
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) All devices 3.8 3.7 3.7 All devices 3.9 3.7 3.7 All devices 64 77 95 All devices 65 79 98 Note 1: 7.7 7.5 7.5 7.9 7.5 7.5 167 193 269 266 294 360 mA mA mA mA mA mA A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 3.3V VDD = 2.5V FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) VDD = 3.3V VDD = 2.5V FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No.
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) All devices 4.2 3.9 3.6 All devices 4.3 4.0 3.7 All devices 4.6 4.3 4.0 All devices 4.7 4.4 4.1 All devices 11.0 10.5 10.0 All devices 12.0 11.5 11.0 Note 1: 8.5 8.0 7.3 8.6 8.1 7.6 9.3 8.7 8.1 9.4 8.8 8.2 22.0 21.0 20.0 24.0 23.0 22.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 3.3V VDD = 2.5V FOSC = 40 MHz (PRI_RUN mode, EC oscillator) VDD = 3.3V VDD = 2.5V FOSC = 4 MHz (PRI_RUN mode, EC oscillator) VDD = 3.3V VDD = 2.5V FOSC = 1 MHz (PRI_RUN mode, EC oscillator) Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No.
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) All devices 6.2 5.7 5.7 All devices 6.6 6.1 6.1 All devices 11.0 10.5 10.0 All devices 12.0 11.5 11.0 Note 1: 14 13 13 15 14 14 22 21 20 24 23 22 mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V FOSC = 4 MHZ, 16 MHZ internal (PRI_RUN HS+PLL) FOSC = 4 MHZ, 16 MHZ internal (PRI_RUN HS+PLL) FOSC = 10 MHZ, 40 MHZ internal (PRI_RUN HS+PLL) FOSC = 10 MHZ, 40 MHZ internal (PRI_RUN HS+PLL) Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No.
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) All devices 150 160 220 All devices 190 200 250 All devices 350 375 420 All devices 410 0.450 0.475 All devices 5.0 5.2 5.5 All devices 5.5 6.0 6.5 Note 1: 337 355 512 518 528 647 737 787 917 954 1.03 1.13 10.1 10.6 11.1 11.1 12.1 13.1 A A A A A A A A A A mA mA mA mA mA mA mA mA -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 3.3V VDD = 2.5V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 3.3V VDD = 2.5V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 3.3V VDD = 2.5V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No.
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2) All devices 4.1 3.8 3.8 All devices 4.1 3.8 3.8 All devices 66 79 97 All devices 67 81 100 Note 1: 8.3 7.7 7.7 8.3 7.7 7.7 169 195 271 268 296 362 mA mA mA mA mA mA A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 3.3V VDD = 2.5V FOSC = 32 kHz (SEC_IDLE mode, Timer1 as clock) VDD = 3.3V VDD = 2.5V FOSC = 32 kHz (SEC_RUN mode, Timer1 as clock) Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No.
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions
PIC18F45J10 Family (Industrial) Param No. D022 (IWDT)
Module Differential Currents (IWDT, IOSCB, IAD) 6.5 A Watchdog Timer 3.2 3.2 6.5 A 5.1 10.3 A 3.5 7.1 A 3.5 5.5 8.4 11.5 13.2 9.6 12.4 14.1 1.0 1.2 7.1 11.2 17 24 30 20 25 29 5 5 A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C to +85C -40C to +85C
VDD = 2.5V
VDD = 3.3V
D025 (IOSCB)
Timer1 Oscillator
VDD = 2.5V
32 kHz on Timer1(3)
VDD = 3.3V VDD = 2.5V VDD = 3.3V
32 kHz on Timer1(3)
D026 (IAD) Note 1:
A/D Converter
A/D on, not converting
2:
3:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost.
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24.3 DC Characteristics: PIC18F45J10 Family (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Input Low Voltage All I/O Ports: D030 D030A D031 D032 D033 D033A D034 VIH with Schmitt Trigger Buffer MCLR OSC1 OSC1 T1CKI Input High Voltage I/O Ports with non 5.5V Tolerance:(4) D040 D040A D041 with Schmitt Trigger Buffer I/O Ports with 5.5V Tolerance:(4) Dxxx DxxxA Dxxx D042 D043 D043A D044 IIL D060 D060A D061 D063 IPU D070 Note 1: 2: IPURB with Schmitt Trigger Buffer MCLR OSC1 OSC1 T1CKI Input Leakage Current(2,3) -- -- -- -- 30 0.2 0.2 0.2 0.2 240 A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN 5.5V, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD VDD = 3.3V, VPIN = VSS I/O Ports with non 5.5V Tolerance(4) I/O Ports with 5.5V Tolerance(4) MCLR OSC1 Weak Pull-up Current PORTB Weak Pull-up Current with TTL Buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.8 VDD 0.7 VDD 0.8 VDD 1.6 5.5 5.5 5.5 VDD VDD VDD VDD V V V V V V V HS, HSPLL modes EC, ECPLL modes VDD < 3.3V 3.3V VDD 3.6V with TTL Buffer 0.25 VDD + 0.8V 2.0 0.8 VDD VDD VDD VDD V V V VDD < 3.3V 3.3V VDD 3.6V with TTL Buffer VSS -- VSS VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD 0.3 V V V V V V V HS, HSPLL modes EC, ECPLL modes(1) VDD < 3.3V 3.3V VDD 3.6V Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 10-2 for the pins that have corresponding tolerance limits.
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24.3 DC Characteristics: PIC18F45J10 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Output Low Voltage I/O Ports (PORTB, PORTC) I/O Ports (PORTA, PORTD, PORTE) D083 VOH D090 OSC2/CLKO (EC mode) Output High Voltage(3) I/O Ports (PORTB, PORTC) I/O Ports (PORTA, PORTD, PORTE) D092 OSC2/CLKO (EC mode) Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 Pin -- 15 pF In HS mode when external clock is used to drive OSC1 To meet the AC Timing Specifications I2CTM Specification 2.4 2.4 2.4 -- -- -- V V V IOH = -6 mA, VDD 3.3V -40C to +85C IOH = -2 mA, VDD 3.3V -40C to +85C IOH = 1.0 mA, VDD 3.3V -40C to +85C -- -- -- 0.4 0.4 0.4 V V V IOL = 8.5 mA, VDD 3.3V -40C to +85C IOL = 3.4 mA, VDD 3.3V -40C to +85C IOL = 1.6 mA, VDD 3.3V -40C to +85C Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VOL D080
D101 D102 Note 1: 2:
CIO CB
All I/O Pins SCLx, SDAx
-- --
50 400
pF pF
3: 4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 10-2 for the pins that have corresponding tolerance limits.
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TABLE 24-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Program Flash Memory D130 D131 EP VPR Cell Endurance VDD for Read Voltage for Self-Timed Erase or Write: VDD VDDCORE D133A TIW D133B TIE D134 D135 Self-Timed Write Cycle Time Self-Timed Page Erased Cycle Time 2.7 2.25 -- -- 20 -- -- -- 2.8 33.0 -- 10 3.6 2.7 -- -- -- -- V V ms ms Year Provided no other specifications are violated mA PIC18FXXJ10 PIC18LFXXJ10 100 VMIN 1K -- -- 3.6 E/W -40C to +85C V VMIN = Minimum operating voltage Min Typ Max Units Conditions DC CHARACTERISTICS Param No. Sym
D132B VPEW
TRETD Characteristic Retention IDDP Supply Current during Programming
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 24-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Param No. D300 D301 D302 D303 D304 D305 * Note 1: Sym VIOFF VICM CMRR TRESP TMC2OV VIRV Characteristics Input Offset Voltage Input Common Mode Voltage* Common Mode Rejection Ratio* Response Time(1)* Comparator Mode Change to Output Valid* Internal Reference Voltage Min -- 0 55 -- -- -- Typ 5.0 -- -- 150 -- 1.2 Max 25 VDD - 1.5 -- 400 10 -- Units mV V dB ns s V Comments
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD.
TABLE 24-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Param No. D310 D311 D312 310 Note 1: Sym VRES VRAA VRUR TSET Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min VDD/24 -- -- -- Typ -- -- 2k -- Max VDD/32 1/2 -- 10 Units LSb LSb s Comments
Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'.
TABLE 24-4:
INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param No. Sym VRGOUT CEFC Characteristics Regulator Output Voltage External Filter Capacitor Value Min -- 4.7 Typ 2.5 10 Max -- -- Units V F Comments
*
Series resistance < 3 Ohm recommended; < 5 Ohm required. These parameters are characterized but not tested. Parameter numbers not yet assigned for these specifications.
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24.4
24.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid High-impedance High Low
SU STO
Setup Stop condition
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24.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 24-5 apply to all timing specifications unless otherwise noted. Figure 24-3 specifies the load conditions for the timing specifications.
TABLE 24-5:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC spec Section 24.1 and Section 24.3.
AC CHARACTERISTICS
FIGURE 24-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 VDD/2 RL Pin VSS Pin VSS CL RL = 464 CL = 50 pF CL = 15 pF for all pins except OSC2/CLKO and including D and E outputs as ports for OSC2/CLK0 CL Load Condition 2
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24.4.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 24-4:
OSC1 1 2 CLKO 3 3 4 4
TABLE 24-6:
Param. No. 1A 1 2 3 4 Note 1:
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Oscillator Frequency
(1)
Symbol FOSC TOSC TCY TOSL, TOSH TOSR, TOSF
Min DC 4 25 25 100 10 --
Max 40 25 -- 250 -- -- 7.5
Units MHz MHz ns ns ns ns ns
Conditions EC Oscillator mode HS Oscillator mode EC Oscillator mode HS Oscillator mode TCY = 4/FOSC, Industrial EC Oscillator mode EC Oscillator mode
External CLKI Period(1) Oscillator Period(1) Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
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TABLE 24-7:
Param No. F10 F11 F12 F13 Sym
PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5V TO 3.6V)
Characteristic Min 4 20 -- -2 Typ -- -- -- -- Max 10 40 2 ms +2 % Units MHz MHz Conditions
FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency RC CLK PLL Start-up Time (lock time) CLKO Stability (Jitter)
Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 24-8:
Param No.
AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL)
Characteristic Min 21.7 Typ -- Max 40.3 Units kHz Conditions
INTRC Accuracy @ Freq = 31 kHz(1) Note 1:
Change of INTRC frequency as VDD core changes.
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FIGURE 24-5: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Note: Refer to Figure 24-3 for load conditions. 15 New Value 19 18 12 16 11 Q1 Q2 Q3
TABLE 24-9:
Param No. 10 11 12 13 14 15 16 17 18 18A 19 20 21 22 23
CLKO AND I/O TIMING REQUIREMENTS
Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 -- -- TCY TCY Typ 75 75 15 15 -- -- -- 50 -- -- -- -- -- -- -- Max 200 200 30 30 0.5 TCY + 20 -- -- 150 -- -- -- 6 5 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
TOSH2CKL OSC1 to CLKO TOSH2CKH OSC1 to CLKO TCKR TCKF CLKO Rise Time CLKO Fall Time
TCKL2IOV CLKO to Port Out Valid TIOV2CKH Port In Valid before CLKO TCKH2IOI TOSH2IOI Port In Hold after CLKO OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid
TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) TIOR TIOF TINP TRBP Port Output Rise Time Port Output Fall Time INTx pin High or Low Time RB<7:4> Change INTx High or Low Time
These parameters are asynchronous events not related to any internal clock edges.
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FIGURE 24-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out Oscillator Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 24-3 for load conditions. 33 32 30
31
34
FIGURE 24-7:
VDD VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable
BROWN-OUT RESET TIMING
BVDD VBGAP = 1.2V
TABLE 24-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Param. Symbol No. 30 31 32 33 34 38 TMCL TWDT TOST TPWRT TIOZ TCSD Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset CPU Start-up Time Min 2 2.8 1024 TOSC 46.2 -- -- Typ -- 4.1 -- 66 2 200 Max -- 5.4 1024 TOSC 85.8 -- -- Units s ms -- ms s s TOSC = OSC1 period Conditions
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FIGURE 24-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 42 T1OSO/T1CKI
41
45 47 TMR0 or TMR1 Note: Refer to Figure 24-3 for load conditions.
46
48
TABLE 24-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param No. 40 41 42 Symbol TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY + 20 10 30 0.5 TCY + 5 10 30 Greater of: 20 ns or (TCY + 40)/N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions
45
TT1H
T1CKI High Time T1CKI Low Time T1CKI Input Period
Synchronous, no prescaler Synchronous, with prescaler Asynchronous Synchronous, no prescaler Synchronous, with prescaler Asynchronous Synchronous
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46
TT1L
47
TT1P
Asynchronous FT1 48 T1CKI Oscillator Input Frequency Range TCKE2TMRI Delay from External T1CKI Clock Edge to Timer Increment
-- 50 7 TOSC
ns kHz --
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FIGURE 24-9: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE)
CCPx (Capture Mode)
50 52
51
CCPx (Compare or PWM Mode) 53 Note: Refer to Figure 24-3 for load conditions. 54
TABLE 24-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE)
Param Symbol No. 50 51 52 53 54 TCCL TCCH TCCP TCCR TCCF Characteristic CCPx Input Low No prescaler Time With prescaler CCPx Input High Time No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 3 TCY + 40 N -- -- Max -- -- -- -- -- 25 25 Units ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
CCPx Input Period CCPx Output Fall Time CCPx Output Fall Time
TABLE 24-13: PARALLEL SLAVE PORT REQUIREMENTS
Param. No. 62 63 64 65 66 Symbol TdtV2wrH TwrH2dtI TrdL2dtV TrdH2dtI TibfINH Characteristic Data In Valid before WR or CS (setup time) WR or CS to Data-In Invalid (hold time) RD and CS to Data-Out Valid RD or CS to Data-Out Invalid Inhibit of the IBF Flag bit being Cleared from WR or CS Min 20 20 -- 10 -- Max -- -- 80 30 3 TCY Units ns ns ns ns Conditions
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FIGURE 24-10:
SSx 70 SCKx (CKP = 0) 71 72 78 79
EXAMPLE SPITM MASTER MODE TIMING (CKE = 0)
SCKx (CKP = 1) 79 MSb 75, 76 SDIx MSb In 74 73 Note: Refer to Figure 24-3 for load conditions. bit 6 - - - - 1 LSb In bit 6 - - - - - - 1 78 LSb
80 SDOx
TABLE 24-14: EXAMPLE SPITM MODE REQUIREMENTS (CKE = 0)
Param No. 70 73 73A 74 75 76 78 79 80 Note 1: Symbol TSSL2SCH, TSSL2SCL TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF Characteristic SSx to SCKx or SCKx Input Setup Time of SDIx Data Input to SCKx Edge Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDIx Data Input to SCKx Edge SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) Min TCY 20 1.5 TCY + 40 40 -- -- -- -- -- Max Units -- -- -- -- 25 25 25 25 50 ns ns ns ns ns ns ns ns ns (Note 1) Conditions
TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV Only if Parameter #71A and #72A are used.
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FIGURE 24-11:
SSx 81 SCKx (CKP = 0) 71 73 SCKx (CKP = 1) 80 78 MSb 75, 76 SDIx MSb In 74 Note: Refer to Figure 24-3 for load conditions. bit 6 - - - - 1 LSb In bit 6 - - - - - - 1 LSb 72 79
EXAMPLE SPITM MASTER MODE TIMING (CKE = 1)
SDOx
TABLE 24-15: EXAMPLE SPITM MODE REQUIREMENTS (CKE = 1)
Param. No. 73 73A 74 75 76 78 79 80 81 Note 1: Symbol TDIV2SCH, TDIV2SCL TB2B TSCH2DIL, TSCL2DIL TDOR TDOF TSCR TSCF Characteristic Setup Time of SDIx Data Input to SCKx Edge Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 Hold Time of SDIx Data Input to SCKx Edge SDOx Data Output Rise Time SDOx Data Output Fall Time SCKx Output Rise Time (Master mode) SCKx Output Fall Time (Master mode) Min 20 1.5 TCY + 40 40 -- -- -- -- -- TCY Max Units -- -- -- 25 25 25 25 50 -- ns ns ns ns ns ns ns ns ns (Note 1) Conditions
TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV TDOV2SCH, SDOx Data Output Setup to SCKx Edge TDOV2SCL Only if Parameter #71A and #72A are used.
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FIGURE 24-12:
SSx 70 SCKx (CKP = 0) 71 72 78 79 83
EXAMPLE SPITM SLAVE MODE TIMING (CKE = 0)
SCKx (CKP = 1) 80 SDOx MSb 75, 76 SDIx SDI MSb In 74 73 Note: Refer to Figure 24-3 for load conditions. bit 6 - - - - 1 LSb In 79 bit 6 - - - - - - 1 78 LSb 77
TABLE 24-16: EXAMPLE SPITM MODE REQUIREMENTS (CKE = 0)
Param No. 70 71 71A 72 72A 73 73A 74 75 76 77 80 83 Note 1: 2: TSCL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25 TCY + 30 40 1.25 TCY + 30 40 20 Max Units Conditions -- -- -- -- -- -- -- -- 25 25 50 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1)
TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSCH SCKx Input High Time (Slave mode) SCKx Input Low Time (Slave mode)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge TDIV2SCL TB2B TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL TDOR TDOF SDOx Data Output Rise Time SDOx Data Output Fall Time
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 40 -- -- 10 -- 1.5 TCY + 40
TSSH2DOZ SSx to SDOx Output High-Impedance TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV TSCH2SSH, SSx after SCKx Edge TSCL2SSH Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used.
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FIGURE 24-13:
SSx 70 83 71 72
EXAMPLE SPITM SLAVE MODE TIMING (CKE = 1)
82
SCKx (CKP = 0)
SCKx (CKP = 1) 80
SDOx
MSb 75, 76
bit 6 - - - - - - 1
LSb 77
SDIx SDI
MSb In
bit 6 - - - - 1
LSb In
Note:
74 Refer to Figure 24-3 for load conditions.
TABLE 24-17: EXAMPLE SPITM SLAVE MODE REQUIREMENTS (CKE = 1)
Param No. 70 71 71A 72 72A 73A 74 75 76 77 80 82 83 TB2B TSCL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25 TCY + 30 40 1.25 TCY + 30 40 20 -- -- 10 -- -- 1.5 TCY + 40 Max Units Conditions -- -- -- -- -- -- -- 25 25 50 50 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 2) (Note 1)
TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSCH SCKx Input High Time (Slave mode) SCKx Input Low Time (Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL TDOR TDOF SDOx Data Output Rise Time SDOx Data Output Fall Time
TSSH2DOZ SSx to SDOx Output High-Impedance TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV TSSL2DOV SDOx Data Output Valid after SSx Edge TSCH2SSH, SSx after SCKx Edge TSCL2SSH Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used.
Note 1: 2:
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FIGURE 24-14: I2CTM BUS START/STOP BITS TIMING
SCLx 90 SDAx
91 92
93
Start Condition
Stop Condition
Note:
Refer to Figure 24-3 for load conditions.
TABLE 24-18: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param. Symbol No. 90 91 92 93 TSU:STA THD:STA TSU:STO Setup Time Start Condition Hold Time Stop Condition Setup Time THD:STO Stop Condition Hold Time Characteristic Start Condition 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
FIGURE 24-15:
I2CTM BUS DATA TIMING
103 100 101 102
SCLx
90 91
106
107 92
SDAx In
110 109 109
SDAx Out Note: Refer to Figure 24-3 for load conditions.
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TABLE 24-19: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE)
Param. No. 100 Symbol THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode MSSP Module 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode MSSP Module 102 TR SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 103 TF SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 90 91 106 107 92 109 110 TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Start Condition Setup Time 100 kHz mode 400 kHz mode Start Condition Hold Time Data Input Hold Time Data Input Setup Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Stop Condition Setup Time 100 kHz mode 400 kHz mode Output Valid from Clock Bus Free Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode D102 Note 1: 2: CB Bus Capacitive Loading Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated CB is specified to be from 10 to 400 pF s s Units s s Conditions
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released.
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FIGURE 24-16: MASTER SSP I2CTM BUS START/STOP BITS TIMING WAVEFORMS
SCLx 90 SDAx
91 92
93
Start Condition Note: Refer to Figure 24-3 for load conditions.
Stop Condition
TABLE 24-20: MASTER SSP I2CTM BUS START/STOP BITS REQUIREMENTS
Param. Symbol No. 90 TSU:STA Characteristic Start Condition Setup Time 91 THD:STA Start Condition Hold Time 92 TSU:STO Stop Condition Setup Time 93 THD:STO Stop Condition Hold Time Note 1: 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) Max -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
Maximum pin capacitance = 10 pF for all I2CTM pins.
FIGURE 24-17:
MASTER SSP I2CTM BUS DATA TIMING
103 100 101 102
SCLx SDAx In
90
91
106
107
92
109
109
110
SDAx Out Note: Refer to Figure 24-3 for load conditions.
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TABLE 24-21: MASTER SSP I2CTM BUS DATA REQUIREMENTS
Param. Symbol No. 100 THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 101 TLOW Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode 102 TR
(1)
Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 -- 250 100 -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 -- --
Max -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400
Units ms ms ms ms ms ms ns ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ns ns ms ms ms ns ns ns ms ms ms pF
Conditions
SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(1) SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(1) Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode
(1)
CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated
103
TF
90
TSU:STA
91
THD:STA Start Condition Hold Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time
106
107
(Note 2)
92
TSU:STO Stop Condition Setup Time TAA Output Valid from Clock Bus Free Time
109
110
TBUF
100 kHz mode 400 kHz mode 1 MHz mode(1)
Time the bus must be free before a new transmission can start
D102 Note 1: 2:
CB
Bus Capacitive Loading
Maximum pin capacitance = 10 pF for all I2CTM pins. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx line is released.
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FIGURE 24-18:
TX/CK pin RX/DT pin 120 Note: Refer to Figure 24-3 for load conditions. 122
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
121
121
TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 121 122 Symbol Characteristic Min Max Units Conditions
TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid TCKRF TDTRF Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time
-- -- --
40 20 20
ns ns ns
FIGURE 24-19:
TX/CK pin RX/DT pin
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Refer to Figure 24-3 for load conditions.
Note:
TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param. No. 125 126 Symbol Characteristic Min Max Units Conditions
TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CK (DT hold time) TCKL2DTL Data Hold after CK (DT hold time)
10 15
-- --
ns ns
(c) 2009 Microchip Technology Inc.
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TABLE 24-24: A/D CONVERTER CHARACTERISTICS: PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL)
Param Symbol No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 A50 NR EIL EDL EOFF EGN -- VREF VREFH VREFL VAIN ZAIN IREF Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage Range (VREFH - VREFL) Reference Voltage High Reference Voltage Low Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) 1.8 3 VSS VSS - 0.3V VREFL -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- Guaranteed(1) -- -- -- -- -- -- -- -- -- -- VREFH VDD - 3.0V VREFH 2.2 5 150 Max 10 <1 <1 <3 <3 Units bit Conditions VREF 3.0V
LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V -- V V V V V k A A During VAIN acquisition. During A/D conversion cycle. VDD < 3.0V VDD 3.0V VSS VAIN VREF
Note 1: 2: 3:
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. Maximum allowed impedance is 8.8 k. This requires higher acquisition time than described in the A/D chapter.
FIGURE 24-20:
A/D CONVERSION TIMING
BSF ADCON0, GO (Note 2) Q4 A/D CLK 132 131 130
A/D DATA
9
8
7
...
...
2
1
0
ADRES ADIF GO
OLD_DATA
NEW_DATA TCY DONE
SAMPLE
SAMPLING STOPPED
Note
1: 2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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TABLE 24-25: A/D CONVERSION REQUIREMENTS
Param Symbol No. 130 131 132 135 TAD TCNV TACQ TSWC Characteristic A/D Clock Period Conversion Time (not including acquisition time) (Note 2) Acquisition Time (Note 3) Switching Time from Convert Sample Min 0.7 11 1.4 -- Max 25.0(1) 12 -- (Note 4) Units s TAD s -40C to +85C Conditions TOSC based, VREF 2.0V
Note 1: 2: 3: 4:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES registers may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock.
(c) 2009 Microchip Technology Inc.
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NOTES:
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25.0
25.1
PACKAGING INFORMATION
Package Marking Information
28-Lead SPDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F24J10 -I/SP e3 0910017
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F24J10-I/SO e3 0910017
28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example PIC18F24J10 -I/SS e3 0910017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
18F24J10 -I/ML e3 0910017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2009 Microchip Technology Inc.
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Package Marking Information (Continued)
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F44J10-I/P e3 0910017
44-Lead QFN
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
18F44J10 -I/ML e3 0910017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
18F45J10 I/PT e3 0910017
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25.2 Package Details
The following sections give the technical details of the packages.
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APPENDIX A: REVISION HISTORY
Revision A (March 2005)
Original data sheet for PIC18F45J10 family devices.
Revision B (November 2006)
Packaging diagrams have been updated.
Revision C (January 2007)
Packaging diagrams have been updated.
Revision D (November 2008)
Electrical characteristics and packaging diagrams have been updated. Minor edits to text throughout document.
Revision E (May 2009)
Pin diagrams have been edited to indicate 5.5V tolerant input pins. Packaging diagrams have been updated. Section 2.0 "Guidelines for Getting Started with PIC18FJ Microcontrollers" has been added. Minor text edits throughout the document.
(c) 2009 Microchip Technology Inc.
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APPENDIX B: MIGRATION BETWEEN HIGH-END DEVICE FAMILIES
migrating an application across device families to achieve a new design goal. These are summarized in Table B-1. The areas of difference which could be a major impact on migration are discussed in greater detail later in this section.
Devices in the PIC18F45J10 family and PIC18F4520 families are very similar in their functions and feature sets. However, there are some potentially important differences which should be considered when
TABLE B-1:
NOTABLE DIFFERENCES BETWEEN PIC18F45J10 AND PIC18F4520 FAMILIES
PIC18F45J10 Family 40 MHz @ 2.15V 2.0V-3.6V Low 1,000 write/erase cycles (typical) PORTB and PORTC only 5.5V on digital only pins 32 PORTB Limited options (EC, HS, fixed 32 kHz INTRC) 10 years (minimum) 156 s/byte (10 ms/64-byte block) Low Voltage, Key Sequence Single block, all or nothing Stored in last 4 words of Program Memory space 200 s (typical) Always on Not available Simple BOR(1) Not available Required Not available Not available Available(2) PIC18F4520 Family 40 MHz @ 4.2V 2.0V-5.5V Lower 100,000 write/erase cycles (typical) All ports VDD on all I/O pins 36 PORTB More options (EC, HS, XT, LP, RC, PLL, flexible INTRC) 40 years (minimum) 15.6 s/byte (1 ms/64-byte block) VPP and LVP Multiple code protection blocks Stored in Configuration Space, starting at 300000h 10 s (typical) Configurable Available Programmable BOR Available Not required Available Available Not available
Characteristic Operating Frequency Supply Voltage Operating Current Program Memory Endurance I/O Sink/Source at 25 mA Input Voltage Tolerance on I/O pins I/O Pull-ups Oscillator Options Program Memory Retention Programming Time (Normalized) Programming Entry Code Protection Configuration Words Start-up Time from Sleep Power-up Timer Data EEPROM Brown-out Reset LVD A/D Calibration In-Circuit Emulation TMR3 Second MSSP Note 1: 2:
Brown-out Reset is not available on PIC18LFXXJ10 devices. Available on 40/44-pin devices only.
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B.1 Power Requirement Differences B.3 Oscillator Differences
The most significant difference between the PIC18F45J10 family and PIC18F4520 device families is the power requirements. PIC18F45J10 family devices are designed on a smaller process; this results in lower maximum voltage and higher leakage current. The operating voltage range for PIC18F45J10 family devices is 2.0V to 3.6V. One of the VDD pins is separated for the core logic supply (VDDCORE). This pin has specific voltage and capacitor requirements as described in Section 24.0 "Electrical Characteristics". The current specifications for PIC18F45J10 family devices are yet to be determined. PIC18F4520 family devices have a greater range of oscillator options than PIC18F45J10 family devices. The latter family is limited primarily to operating modes that support HS and EC oscillators. In addition, the PIC18F45J10 family has an internal RC oscillator with only a fixed 32 kHz output. The higher frequency RC modes of the PIC18F4520 family are not available.
B.4
Peripherals
B.2
Pin Differences
The PIC18F45J10 family is able to operate at 40 MHz down to 2.15 volts unlike the PIC18F4520 family where 40 MHz operation is limited to 4.2 +V applications. Peripherals must also be considered when making a conversion between the PIC18F45J10 family and the PIC18F4520 families: * Data EEPROM: PIC18F45J10 family devices do not have this module. * BOR: PIC18F45J10 family devices do not have a programmable BOR. Simple brown-out capability is provided through the use of the internal voltage regulator (not available in PIC18LFXXJ10 devices). * LVD: PIC18F45J10 family devices do not have this module. * Timer3 (TMR3) has been removed from the PIC18F45J10 family. * The T0CKI/C1OUT pins have been moved from RA4 to RB5. * The 40/44-pin devices in the PIC18F45J10 family have a second MSSP module available on pins RD<3:0>.
There are several differences in the pinouts between the PIC18F45J10 family and the PIC18F4520 families: * Input voltage tolerance * Output current capabilities * Available I/O Pins on the PIC18F45J10 family that have digital only input capability will tolerate voltages up to 5.5V and are thus tolerant to voltages above VDD. Table 10-1 in Section 10.0 "I/O Ports" contains the complete list. In addition to input differences, there are output differences as well. Not all I/O pins can source or sink equal levels of current. Only PORTB and PORTC support the 25 mA source/sink capability that is supported by all output pins on the PIC18F4520. Table 10-2 in Section 10.0 "I/O Ports" contains the complete list of output capabilities. There are additional differences in how some pin functions are implemented on PIC18F45J10 family devices. First, the OSC1/OSC2 oscillator pins are strictly dedicated to the external oscillator function; there is no option to re-allocate these pins to I/O (RA6 or RA7) as on PIC18F4520 devices. Second, the MCLR pin is dedicated only to MCLR and cannot be configured as an input (RE3). Finally, RA4 does not exist on PIC18F45J10 family devices. All of these pin differences (including power pin differences) should be accounted for when making a conversion between PIC18F4520 and PIC18F45J10 family devices.
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NOTES:
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INDEX
A
A/D ................................................................................... 215 A/D Converter Interrupt, Configuring ....................... 219 Acquisition Requirements ........................................ 220 ADCAL Bit ................................................................ 223 ADCON0 Register .................................................... 215 ADCON1 Register .................................................... 215 ADCON2 Register .................................................... 215 ADRESH Register ............................................ 215, 218 ADRESL Register .................................................... 215 Analog Port Pins, Configuring .................................. 221 Associated Registers ............................................... 223 Automatic Acquisition Time ...................................... 221 Calculating the Minimum Required Acquisition Time .............................................. 220 Calibration ................................................................ 223 Configuring the Module ............................................ 219 Conversion Clock (TAD) ........................................... 221 Conversion Status (GO/DONE Bit) .......................... 218 Conversions ............................................................. 222 Converter Characteristics ........................................ 334 Operation in Power-Managed Modes ...................... 223 Special Event Trigger (ECCP) ......................... 136, 222 Use of the ECCP2 Trigger ....................................... 222 Absolute Maximum Ratings ............................................. 303 AC (Timing) Characteristics ............................................. 317 Load Conditions for Device Timing Specifications ...................................... 318 Parameter Symbology ............................................. 317 Temperature and Voltage Specifications ................. 318 Timing Conditions .................................................... 318 Access Bank Mapping with Indexed Literal Offset Mode ................. 70 ACKSTAT ........................................................................ 182 ACKSTAT Status Flag ..................................................... 182 ADCAL Bit ........................................................................ 223 ADCON0 Register ............................................................ 215 GO/DONE Bit ........................................................... 218 ADCON1 Register ............................................................ 215 ADCON2 Register ............................................................ 215 ADDFSR .......................................................................... 292 ADDLW ............................................................................ 255 ADDULNK ........................................................................ 292 ADDWF ............................................................................ 255 ADDWFC ......................................................................... 256 ADRESH Register ............................................................ 215 ADRESL Register .................................................... 215, 218 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 256 ANDWF ............................................................................ 257 Assembler MPASM Assembler .................................................. 300 Auto-Wake-up on Sync Break Character ......................... 206 Block Diagrams A/D ........................................................................... 218 Analog Input Model .................................................. 219 Baud Rate Generator .............................................. 178 Capture Mode Operation ......................................... 129 Comparator Analog Input Model .............................. 229 Comparator I/O Operating Modes ........................... 226 Comparator Output .................................................. 228 Comparator Voltage Reference ............................... 232 Comparator Voltage Reference Output Buffer Example ................................................ 233 Compare Mode Operation ....................................... 130 Device Clock .............................................................. 30 Enhanced PWM ....................................................... 137 EUSART Receive .................................................... 205 EUSART Transmit ................................................... 203 External Power-on Reset Circuit (Slow VDD Power-up) ........................................ 43 Fail-Safe Clock Monitor ........................................... 245 Generic I/O Port Operation ........................................ 97 Interrupt Logic ............................................................ 84 MSSP (I2C Master Mode) ........................................ 176 MSSP (I2C Mode) .................................................... 159 MSSP (SPI Mode) ................................................... 149 On-Chip Reset Circuit ................................................ 41 PIC18F24J10/25J10 .................................................. 10 PIC18F44J10/45J10 .................................................. 11 PLL ............................................................................ 29 PORTD and PORTE (Parallel Slave Port) ............... 113 PWM Operation (Simplified) .................................... 132 Reads from Flash Program Memory ......................... 75 Single Comparator ................................................... 227 Table Read Operation ............................................... 71 Table Write Operation ............................................... 72 Table Writes to Flash Program Memory .................... 77 Timer0 in 16-Bit Mode ............................................. 116 Timer0 in 8-Bit Mode ............................................... 116 Timer1 ..................................................................... 120 Timer1 (16-Bit Read/Write Mode) ............................ 121 Timer2 ..................................................................... 126 Watchdog Timer ...................................................... 242 BN .................................................................................... 258 BNC ................................................................................. 259 BNN ................................................................................. 259 BNOV .............................................................................. 260 BNZ ................................................................................. 260 BOR. See Brown-out Reset. BOV ................................................................................. 263 BRA ................................................................................. 261 Break Character (12-Bit) Transmit and Receive .............. 208 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 43 and On-Chip Voltage Regulator .............................. 243 Disabling in Sleep Mode ............................................ 43 BSF .................................................................................. 261 BTFSC ............................................................................. 262 BTFSS ............................................................................. 262 BTG ................................................................................. 263 BZ .................................................................................... 264
B
Bank Select Register (BSR) ............................................... 58 Baud Rate Generator ....................................................... 178 BC .................................................................................... 257 BCF .................................................................................. 258 BF .................................................................................... 182 BF Status Flag ................................................................. 182
C
C Compilers MPLAB C18 ............................................................. 300 MPLAB C30 ............................................................. 300
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Calibration (A/D Converter) .............................................. 223 CALL ................................................................................ 264 CALLW ............................................................................. 293 Capture (CCP Module) ..................................................... 129 Associated Registers ............................................... 131 CCP Pin Configuration ............................................. 129 CCPRxH:CCPRxL Registers ................................... 129 Prescaler .................................................................. 129 Software Interrupt .................................................... 129 Capture (ECCP Module) .................................................. 136 Capture/Compare/PWM (CCP) ........................................ 127 Capture Mode. See Capture. CCP Modules and Timer Resources ....................... 128 CCPRxH Register .................................................... 128 CCPRxL Register ..................................................... 128 Compare Mode. See Compare. Interactions Between ECCP1/CCP1 and CCP2 for Timer Resources .............................. 128 Module Configuration ............................................... 128 Clock Sources .................................................................... 30 Default System Clock on Reset ................................. 31 Selection Using OSCCON Register ........................... 31 CLRF ................................................................................ 265 CLRWDT .......................................................................... 265 Code Examples 16 x 16 Signed Multiply Routine ................................ 82 16 x 16 Unsigned Multiply Routine ............................ 82 8 x 8 Signed Multiply Routine .................................... 81 8 x 8 Unsigned Multiply Routine ................................ 81 Changing Between Capture Prescalers ................... 129 Computed GOTO Using an Offset Value ................... 55 Erasing a Flash Program Memory Row ..................... 76 Fast Register Stack .................................................... 55 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 66 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ............................... 124 Initializing PORTA ...................................................... 98 Initializing PORTB .................................................... 101 Initializing PORTC .................................................... 104 Initializing PORTD .................................................... 107 Initializing PORTE .................................................... 110 Loading the SSP1BUF (SSP1SR) Register ............. 152 Reading a Flash Program Memory Word .................. 75 Saving STATUS, WREG and BSR Registers in RAM ....................................... 95 Writing to Flash Program Memory ............................. 78 Code Protection ............................................................... 235 COMF ............................................................................... 266 Comparator ...................................................................... 225 Analog Input Connection Considerations ................. 229 Associated Registers ............................................... 229 Configuration ............................................................ 226 Effects of a Reset ..................................................... 228 Interrupts .................................................................. 228 Operation ................................................................. 227 Operation During Sleep ........................................... 228 Outputs .................................................................... 227 Reference ................................................................ 227 External Signal ................................................. 227 Internal Signal .................................................. 227 Response Time ........................................................ 227 Comparator Specifications ............................................... 316 Comparator Voltage Reference ....................................... 231 Accuracy and Error .................................................. 232 Associated Registers ............................................... 233 Configuring .............................................................. 231 Connection Considerations ...................................... 232 Effects of a Reset .................................................... 232 Operation During Sleep ........................................... 232 Compare (CCP Module) .................................................. 130 Associated Registers ............................................... 131 CCPRx Register ...................................................... 130 Pin Configuration ..................................................... 130 Software Interrupt .................................................... 130 Special Event Trigger .............................................. 130 Timer1 Mode Selection ............................................ 130 Compare (ECCP Module) ................................................ 136 Special Event Trigger ...................................... 136, 222 Computed GOTO ............................................................... 55 Configuration Bits ............................................................ 235 Configuration Register Protection .................................... 247 Context Saving During Interrupts ....................................... 95 CPFSEQ .......................................................................... 266 CPFSGT .......................................................................... 267 CPFSLT ........................................................................... 267 Crystal Oscillator/Ceramic Resonator ................................ 27 Customer Change Notification Service ............................ 363 Customer Notification Service ......................................... 363 Customer Support ............................................................ 363
D
Data Addressing Modes .................................................... 66 Comparing Addressing Modes with the Extended Instruction Set Enabled ..................... 69 Direct ......................................................................... 66 Indexed Literal Offset ................................................ 68 Instructions Affected .......................................... 68 Indirect ....................................................................... 66 Inherent and Literal .................................................... 66 Data Memory ..................................................................... 58 Access Bank .............................................................. 60 and the Extended Instruction Set .............................. 68 Bank Select Register (BSR) ...................................... 58 General Purpose Registers ....................................... 60 Map for PIC18F45J10 Family .................................... 59 Special Function Registers ........................................ 61 DAW ................................................................................ 268 DC Characteristics ........................................................... 313 Power-Down and Supply Current ............................ 306 Supply Voltage ........................................................ 305 DCFSNZ .......................................................................... 269 DECF ............................................................................... 268 DECFSZ .......................................................................... 269 Default System Clock ........................................................ 31 Development Support ...................................................... 299 Device Overview .................................................................. 7 Core Features .............................................................. 7 Details on Individual Family Members ......................... 8 Features (table) ........................................................... 9 Other Special Features ................................................ 8 Direct Addressing .............................................................. 67
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E
Effect on Standard PIC Instructions ................................. 296 Effects of Power-Managed Modes on Various Clock Sources ............................................... 32 Electrical Characteristics .................................................. 303 Enhanced Capture/Compare/PWM (ECCP) .................... 135 Associated Registers ............................................... 148 Capture and Compare Modes .................................. 136 Capture Mode. See Capture (ECCP Module). Outputs and Configuration ....................................... 136 Pin Configurations for ECCP1 Modes ...................... 136 PWM Mode. See PWM (ECCP Module). Standard PWM Mode ............................................... 136 Timer Resources ...................................................... 136 Enhanced PWM Mode. See PWM (ECCP Module). ........ 137 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 220 A/D Minimum Charging Time ................................... 220 Errata ................................................................................... 6 EUSART Asynchronous Mode ................................................ 203 12-Bit Break Transmit and Receive ................. 208 Associated Registers, Receive ........................ 206 Associated Registers, Transmit ....................... 204 Auto-Wake-up on Sync Break ......................... 206 Receiver ........................................................... 205 Setting Up 9-Bit Mode with Address Detect ........................................ 205 Transmitter ....................................................... 203 Baud Rate Generator Operation in Power-Managed Mode ................ 197 Baud Rate Generator (BRG) .................................... 197 Associated Registers ....................................... 198 Auto-Baud Rate Detect .................................... 201 Baud Rate Error, Calculating ........................... 198 Baud Rates, Asynchronous Modes ................. 199 High Baud Rate Select (BRGH Bit) ................. 197 Sampling .......................................................... 197 Synchronous Master Mode ...................................... 209 Associated Registers, Receive ........................ 211 Associated Registers, Transmit ....................... 210 Reception ......................................................... 211 Transmission ................................................... 209 Synchronous Slave Mode ........................................ 212 Associated Registers, Receive ........................ 213 Associated Registers, Transmit ....................... 212 Reception ......................................................... 213 Transmission ................................................... 212 Extended Instruction Set ADDFSR .................................................................. 292 ADDULNK ................................................................ 292 and Using MPLAB IDE Tools ................................... 298 CALLW ..................................................................... 293 Considerations for Use ............................................ 296 MOVSF .................................................................... 293 MOVSS .................................................................... 294 PUSHL ..................................................................... 294 SUBFSR .................................................................. 295 SUBULNK ................................................................ 295 Syntax ...................................................................... 291 External Clock Input (EC Modes) ....................................... 28
F
Fail-Safe Clock Monitor ........................................... 235, 245 Interrupts in Power-Managed Modes ...................... 246 POR or Wake-up from Sleep ................................... 246 WDT During Oscillator Failure ................................. 245 Fast Register Stack ........................................................... 55 Firmware Instructions ...................................................... 249 Flash Configuration Words .............................................. 235 Flash Program Memory ..................................................... 71 Associated Registers ................................................. 79 Control Registers ....................................................... 72 EECON1 and EECON2 ..................................... 72 TABLAT (Table Latch) ....................................... 74 TBLPTR (Table Pointer) .................................... 74 Erase Sequence ........................................................ 76 Erasing ...................................................................... 76 Operation During Code-Protect ................................. 79 Reading ..................................................................... 75 Table Pointer Boundaries Based on Operation ....................... 74 Table Pointer Boundaries .......................................... 74 Table Reads and Table Writes .................................. 71 Write Sequence ......................................................... 77 Writing To .................................................................. 77 Protection Against Spurious Writes ................... 79 Unexpected Termination ................................... 79 Write Verify ........................................................ 79 FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 270
H
Hardware Multiplier ............................................................ 81 Introduction ................................................................ 81 Operation ................................................................... 81 Performance Comparison .......................................... 81
I
I/O Ports ............................................................................ 97 I2C Mode (MSSP) Acknowledge Sequence Timing .............................. 185 Associated Registers ............................................... 192 Baud Rate Generator .............................................. 178 Bus Collision During a Repeated Start Condition .................. 190 During a Stop Condition .................................. 191 Clock Arbitration ...................................................... 179 Clock Stretching ...................................................... 171 10-Bit Slave Receive Mode (SEN = 1) ............ 171 10-Bit Slave Transmit Mode ............................ 171 7-Bit Slave Receive Mode (SEN = 1) .............. 171 7-Bit Slave Transmit Mode .............................. 171 Clock Synchronization and the CKP Bit .................. 172 Effects of a Reset .................................................... 186 General Call Address Support ................................. 175 I2C Clock Rate w/BRG ............................................ 178 Master Mode ............................................................ 176 Baud Rate Generator ...................................... 178 Operation ......................................................... 177 Reception ........................................................ 182 Repeated Start Condition Timing .................... 181 Start Condition Timing ..................................... 180 Transmission ................................................... 182
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Multi-Master Communication, Bus Collision and Arbitration .................................................. 186 Multi-Master Mode ................................................... 186 Operation ................................................................. 164 Read/Write Bit Information (R/W Bit) ............... 164, 166 Registers .................................................................. 159 Serial Clock (SCKx/SCLx) ....................................... 166 Slave Mode .............................................................. 164 Addressing ....................................................... 164 Reception ......................................................... 166 Transmission .................................................... 166 Sleep Operation ....................................................... 186 Stop Condition Timing .............................................. 185 INCF ................................................................................. 270 INCFSZ ............................................................................ 271 In-Circuit Debugger .......................................................... 247 In-Circuit Serial Programming (ICSP) ...................... 235, 247 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 296 Indexed Literal Offset Mode ............................................. 296 Indirect Addressing ............................................................ 67 INFSNZ ............................................................................ 271 Initialization Conditions for All Registers ...................... 47-50 Instruction Cycle ................................................................. 56 Clocking Scheme ....................................................... 56 Instruction Flow/Pipelining ................................................. 56 Instruction Set .................................................................. 249 ADDLW .................................................................... 255 ADDWF .................................................................... 255 ADDWF (Indexed Literal Offset Mode) .................... 297 ADDWFC ................................................................. 256 ANDLW .................................................................... 256 ANDWF .................................................................... 257 BC ............................................................................ 257 BCF .......................................................................... 258 BN ............................................................................ 258 BNC ......................................................................... 259 BNN ......................................................................... 259 BNOV ....................................................................... 260 BNZ .......................................................................... 260 BOV ......................................................................... 263 BRA .......................................................................... 261 BSF .......................................................................... 261 BSF (Indexed Literal Offset Mode) .......................... 297 BTFSC ..................................................................... 262 BTFSS ..................................................................... 262 BTG .......................................................................... 263 BZ ............................................................................ 264 CALL ........................................................................ 264 CLRF ........................................................................ 265 CLRWDT .................................................................. 265 COMF ...................................................................... 266 CPFSEQ .................................................................. 266 CPFSGT .................................................................. 267 CPFSLT ................................................................... 267 DAW ......................................................................... 268 DCFSNZ .................................................................. 269 DECF ....................................................................... 268 DECFSZ ................................................................... 269 Extended Instruction Set .......................................... 291 General Format ........................................................ 251 GOTO ...................................................................... 270 INCF ......................................................................... 270 INCFSZ .................................................................... 271 INFSNZ .................................................................... 271 IORLW ..................................................................... 272 IORWF ..................................................................... 272 LFSR ....................................................................... 273 MOVF ...................................................................... 273 MOVFF .................................................................... 274 MOVLB .................................................................... 274 MOVLW ................................................................... 275 MOVWF ................................................................... 275 MULLW .................................................................... 276 MULWF .................................................................... 276 NEGF ....................................................................... 277 NOP ......................................................................... 277 Opcode Field Descriptions ....................................... 250 POP ......................................................................... 278 PUSH ....................................................................... 278 RCALL ..................................................................... 279 RESET ..................................................................... 279 RETFIE .................................................................... 280 RETLW .................................................................... 280 RETURN .................................................................. 281 RLCF ....................................................................... 281 RLNCF ..................................................................... 282 RRCF ....................................................................... 282 RRNCF .................................................................... 283 SETF ....................................................................... 283 SETF (Indexed Literal Offset Mode) ........................ 297 SLEEP ..................................................................... 284 Standard Instructions ............................................... 249 SUBFWB ................................................................. 284 SUBLW .................................................................... 285 SUBWF .................................................................... 285 SUBWFB ................................................................. 286 SWAPF .................................................................... 286 TBLRD ..................................................................... 287 TBLWT .................................................................... 288 TSTFSZ ................................................................... 289 XORLW ................................................................... 289 XORWF ................................................................... 290 INTCON Registers ............................................................. 85 Inter-Integrated Circuit. See I2C Mode. Internal Oscillator Block ..................................................... 30 Internal RC Oscillator Use with WDT .......................................................... 242 Internet Address .............................................................. 363 Interrupt Sources ............................................................. 235 A/D Conversion Complete ....................................... 219 Capture Complete (CCP) ......................................... 129 Compare Complete (CCP) ....................................... 130 Interrupt-on-Change (RB7:RB4) .............................. 101 INTx Pin ..................................................................... 95 PORTB, Interrupt-on-Change .................................... 95 TMR0 ......................................................................... 95 TMR0 Overflow ........................................................ 117 TMR1 Overflow ........................................................ 119 TMR2-to-PR2 Match (PWM) ............................ 132, 137 Interrupts ............................................................................ 83 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ................................................. 101 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 272 IORWF ............................................................................. 272 IPR Registers ..................................................................... 92
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L
LFSR ................................................................................ 273
P
Packaging Information ..................................................... 337 Details ...................................................................... 339 Marking .................................................................... 337 Parallel Slave Port (PSP) ......................................... 107, 113 Associated Registers ............................................... 114 CS (Chip Select) ...................................................... 113 PORTD .................................................................... 113 RD (Read Input) ...................................................... 113 Select (PSPMODE Bit) .................................... 107, 113 WR (Write Input) ...................................................... 113 PICSTART Plus Development Programmer .................... 302 PIE Registers ..................................................................... 90 Pin Functions MCLR .................................................................. 12, 16 OSC1/CLKI .......................................................... 12, 16 OSC2/CLKO ........................................................ 12, 16 RA0/AN0 .............................................................. 13, 17 RA1/AN1 .............................................................. 13, 17 RA2/AN2/VREF-/CVREF ....................................... 13, 17 RA3/AN3/VREF+ .................................................. 13, 17 RA5/AN4/SS1/C2OUT ......................................... 13, 17 RB0/INT0/FLT0/AN12 ......................................... 14, 18 RB1/INT1/AN10 ................................................... 14, 18 RB2/INT2/AN8 ..................................................... 14, 18 RB3/AN9/CCP2 ................................................... 14, 18 RB4/KBI0/AN11 ................................................... 14, 18 RB5/KBI1/C1OUT ...................................................... 18 RB5/KBI1/T0CKI/C1OUT .......................................... 14 RB6/KBI2/PGC .................................................... 14, 18 RB7/KBI3/PGD .................................................... 14, 18 RC0/T1OSO/T1CKI ............................................. 15, 19 RC1/T1OSI/CCP2 ............................................... 15, 19 RC2/CCP1 ................................................................. 15 RC2/CCP1/P1A ......................................................... 19 RC3/SCK1/SCL1 ................................................. 15, 19 RC4/SDI1/SDA1 .................................................. 15, 19 RC5/SDO1 ........................................................... 15, 19 RC6/TX/CK .......................................................... 15, 19 RC7/RX/DT .......................................................... 15, 19 RD0/PSP0/SCK2/SCL2 ............................................. 20 RD1/PSP1/SDI2/SDA2 .............................................. 20 RD2/PSP2/SDO2 ...................................................... 20 RD3/PSP3/SS2 ......................................................... 20 RD4/PSP4 ................................................................. 20 RD5/PSP5/P1B ......................................................... 20 RD6/PSP6/P1C ......................................................... 20 RD7/PSP7/P1D ......................................................... 20 RE0/RD/AN5 ............................................................. 21 RE1/WR/AN6 ............................................................. 21 RE2/CS/AN7 .............................................................. 21 VDD ...................................................................... 15, 21 VDDCORE/VCAP .................................................... 15, 21 VSS ...................................................................... 15, 21 Pinout I/O Descriptions PIC18F24J10/25J10 .................................................. 12 PIC18F44J10/45J10 .................................................. 16 PIR Registers ..................................................................... 88 PLL Frequency Multiplier ................................................... 29 ECPLL Oscillator Mode ............................................. 29 HSPLL Oscillator Mode ............................................. 29 POP ................................................................................. 278 POR. See Power-on Reset.
M
Master Clear (MCLR) ......................................................... 43 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ......................................................... 51 Data Memory ............................................................. 58 Program Memory ....................................................... 51 Memory Programming Requirements .............................. 315 Microchip Internet Web Site ............................................. 363 MOVF ............................................................................... 273 MOVFF ............................................................................ 274 MOVLB ............................................................................ 274 MOVLW ........................................................................... 275 MOVSF ............................................................................ 293 MOVSS ............................................................................ 294 MOVWF ........................................................................... 275 MPLAB ASM30 Assembler, Linker, Librarian .................. 300 MPLAB ICD 2 In-Circuit Debugger .................................. 301 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 301 MPLAB Integrated Development Environment Software .............................................. 299 MPLAB PM3 Device Programmer ................................... 301 MPLAB REAL ICE In-Circuit Emulator System ................ 301 MPLINK Object Linker/MPLIB Object Librarian ............... 300 MSSP ACK Pulse ........................................................ 164, 166 Control Registers (general) ...................................... 149 I2C Mode. See I2C Mode. Module Overview ..................................................... 149 SPI Master/Slave Connection .................................. 153 SSPxBUF Register .................................................. 154 SSPxSR Register ..................................................... 154 MULLW ............................................................................ 276 MULWF ............................................................................ 276
N
NEGF ............................................................................... 277 NOP ................................................................................. 277 Notable Differences Between PIC18F4520 and PIC18F45J10 Families ...................................... 350 Oscillator Options ..................................................... 351 Peripherals ............................................................... 351 Pinouts ..................................................................... 351 Power Requirements ............................................... 351
O
Oscillator Configuration ...................................................... 27 EC .............................................................................. 27 ECPLL ........................................................................ 27 HS .............................................................................. 27 HS Modes .................................................................. 27 HSPLL ........................................................................ 27 Internal Oscillator Block ............................................. 30 INTRC ........................................................................ 27 Oscillator Selection .......................................................... 235 Oscillator Start-up Timer (OST) ......................................... 33 Oscillator Switching ............................................................ 30 Oscillator Transitions ......................................................... 31 Oscillator, Timer1 ............................................................. 119
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PORTA Associated Registers ............................................... 100 LATA Register ............................................................ 98 PORTA Register ........................................................ 98 TRISA Register .......................................................... 98 PORTB Associated Registers ............................................... 103 LATB Register .......................................................... 101 PORTB Register ...................................................... 101 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 101 TRISB Register ........................................................ 101 PORTC Associated Registers ............................................... 106 LATC Register ......................................................... 104 PORTC Register ...................................................... 104 RC3/SCK1/SCL1 Pin ............................................... 166 TRISC Register ........................................................ 104 PORTD Associated Registers ............................................... 109 LATD Register ......................................................... 107 Parallel Slave Port (PSP) Function .......................... 107 PORTD Register ...................................................... 107 TRISD Register ........................................................ 107 PORTE Associated Registers ............................................... 112 LATE Register .......................................................... 110 PORTE Register ...................................................... 110 PSP Mode Select (PSPMODE Bit) .......................... 107 TRISE Register ........................................................ 110 Power-Managed Modes ..................................................... 35 and EUSART Operation ........................................... 197 and Multiple Sleep Commands .................................. 36 and PWM Operation ................................................ 147 and SPI Operation ................................................... 157 Clock Transitions and Status Indicators ..................... 36 Entering ...................................................................... 35 Exiting Idle and Sleep Modes .................................... 40 by Reset ............................................................. 40 by WDT Time-out ............................................... 40 Without an Oscillator Start-up Delay .................. 40 Idle Modes ................................................................. 38 PRI_IDLE ........................................................... 39 RC_IDLE ............................................................ 40 SEC_IDLE .......................................................... 39 Run Modes ................................................................. 36 PRI_RUN ........................................................... 36 RC_RUN ............................................................ 37 SEC_RUN .......................................................... 36 Selecting .................................................................... 35 Sleep Mode ................................................................ 38 Summary (table) ........................................................ 35 Power-on Reset (POR) ...................................................... 43 Power-up Timer (PWRT) ........................................... 44 Time-out Sequence .................................................... 44 Power-up Delays ................................................................ 33 Power-up Timer (PWRT) .............................................. 33, 44 Prescaler Timer2 ...................................................................... 138 Prescaler, Timer0 ............................................................. 117 Prescaler, Timer2 ............................................................. 133 PRI_IDLE Mode ................................................................. 39 PRI_RUN Mode ................................................................. 36 Program Counter ................................................................ 53 PCL, PCH and PCU Registers ................................... 53 PCLATH and PCLATU Registers .............................. 53 Program Memory and Extended Instruction Set .................................... 70 Flash Configuration Words ........................................ 52 Instructions ................................................................ 57 Two-Word .......................................................... 57 Interrupt Vector .................................................... 51, 52 Look-up Tables .......................................................... 55 Map and Stack (diagram) .......................................... 51 Memory Maps Hard Vectors and Configuration Words ............. 52 Reset Vector ........................................................ 51, 52 Program Verification and Code Protection ...................... 247 Programming, Device Instructions ................................... 249 PSP. See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 278 PUSH and POP Instructions .............................................. 54 PUSHL ............................................................................. 294 PWM (CCP Module) Associated Registers ............................................... 134 Auto-Shutdown (CCP1 Only) ................................... 133 CCPR1H:CCPR1L Registers ................................... 137 Duty Cycle ....................................................... 132, 138 Example Frequencies/Resolutions .................. 133, 138 Period .............................................................. 132, 137 Setup for Operation ................................................. 133 TMR2-to-PR2 Match ........................................ 132, 137 PWM (ECCP Module) ...................................................... 137 Direction Change in Full-Bridge Output Mode ......... 142 Effects of a Reset .................................................... 147 Enhanced PWM Auto-Shutdown ............................. 144 Full-Bridge Application Example .............................. 142 Full-Bridge Mode ..................................................... 141 Half-Bridge Mode ..................................................... 140 Half-Bridge Output Mode Applications Example ...... 140 Operation in Power-Managed Modes ...................... 147 Operation with Fail-Safe Clock Monitor ................... 147 Output Configurations .............................................. 138 Output Relationships (Active-High) .......................... 139 Output Relationships (Active-Low) .......................... 139 Programmable Dead-Band Delay ............................ 144 Setup for PWM Operation ........................................ 147 Start-up Considerations ........................................... 146
Q
Q Clock .................................................................... 133, 138
R
RAM. See Data Memory. RBIF Bit ........................................................................... 101 RC_IDLE Mode .................................................................. 40 RC_RUN Mode .................................................................. 37 RCALL ............................................................................. 279 RCON Register Bit Status During Initialization .................................... 46 Reader Response ............................................................ 364 Register File ....................................................................... 60 Register File Summary ................................................ 62-64 Registers ADCON0 (A/D Control 0) ......................................... 215 ADCON1 (A/D Control 1) ......................................... 216 ADCON2 (A/D Control 2) ......................................... 217 BAUDCON (Baud Rate Control) .............................. 196 CCP1CON (ECCP1 Control) ................................... 135 CCPxCON (CCPx Control) ...................................... 127
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CMCON (Comparator Control) ................................ 225 CONFIG1H (Configuration 1 High) .......................... 237 CONFIG1L (Configuration 1 Low) ............................ 237 CONFIG2H (Configuration 2 High) .......................... 239 CONFIG2L (Configuration 2 Low) ............................ 238 CONFIG3H (Configuration 3 High) .......................... 240 CONFIG3L (Configuration 3 Low) ............................ 240 CVRCON (Comparator Voltage Reference Control) .......................................... 231 DEVID1 (Device ID Register 1) ................................ 241 DEVID2 (Device ID Register 2) ................................ 241 ECCP1DEL (PWM Dead-Band Delay) .................... 144 EECON1 (EEPROM Control 1) .................................. 73 EUSART Receive Status and Control ...................... 195 INTCON (Interrupt Control) ........................................ 85 INTCON2 (Interrupt Control 2) ................................... 86 INTCON3 (Interrupt Control 3) ................................... 87 IPR1 (Peripheral Interrupt Priority 1) .......................... 92 IPR2 (Peripheral Interrupt Priority 2) .......................... 93 IPR3 (Peripheral Interrupt Priority 3) .......................... 93 OSCCON (Oscillator Control) .................................... 32 OSCTUNE (PLL Control) ........................................... 29 PIE1 (Peripheral Interrupt Enable 1) .......................... 90 PIE2 (Peripheral Interrupt Enable 2) .......................... 91 PIE3 (Peripheral Interrupt Enable 3) .......................... 91 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 88 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 89 PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 89 RCON (Reset Control) ......................................... 42, 94 SSPxCON1 (MSSPx Control 1, I2C Mode) .............. 161 SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 151 SSPxCON2 (MSSPx Control 2, I2C Master Mode) ............................................ 162 SSPxCON2 (MSSPx Control 2, I2C Slave Mode) .............................................. 163 SSPxSTAT (MSSPx Status, I2C Mode) ................... 160 SSPxSTAT (MSSPx Status, SPI Mode) .................. 150 STATUS ..................................................................... 65 STKPTR (Stack Pointer) ............................................ 54 T0CON (Timer0 Control) .......................................... 115 T1CON (Timer1 Control) .......................................... 119 T2CON (Timer2 Control) .......................................... 125 TRISE (PORTE/PSP Control) .................................. 111 TXSTA (EUSART Transmit Status and Control) ..................................................... 194 WDTCON (Watchdog Timer Control) ...................... 242 RESET ............................................................................. 279 Reset Brown-out Reset (BOR) ............................................. 41 Configuration Mismatch (CM) .................................... 41 MCLR Reset, During Power-Managed Modes ........... 41 MCLR Reset, Normal Operation ................................ 41 Power-on Reset (POR) .............................................. 41 RESET Instruction ..................................................... 41 Stack Full Reset ......................................................... 41 Stack Underflow Reset .............................................. 41 Watchdog Timer (WDT) Reset ................................... 41 Resets .............................................................................. 235 Brown-out Reset (BOR) ........................................... 235 Oscillator Start-up Timer (OST) ............................... 235 Power-on Reset (POR) ............................................ 235 Power-up Timer (PWRT) ......................................... 235 RETFIE ............................................................................ 280 RETLW ............................................................................ 280 RETURN .......................................................................... 281 Return Address Stack ........................................................ 53 Return Stack Pointer (STKPTR) ........................................ 54 Revision History ............................................................... 349 RLCF ............................................................................... 281 RLNCF ............................................................................. 282 RRCF ............................................................................... 282 RRNCF ............................................................................ 283
S
SCKx ............................................................................... 149 SDIx ................................................................................. 149 SDOx ............................................................................... 149 SEC_IDLE Mode ............................................................... 39 SEC_RUN Mode ................................................................ 36 Serial Clock, SCKx .......................................................... 149 Serial Data In (SDIx) ........................................................ 149 Serial Data Out (SDOx) ................................................... 149 Serial Peripheral Interface. See SPI Mode. SETF ............................................................................... 283 Slave Select (SSx) ........................................................... 149 SLEEP ............................................................................. 284 Sleep OSC1 and OSC2 Pin States ...................................... 33 Software Simulator (MPLAB SIM) ................................... 300 Special Event Trigger. See Compare (ECCP Module). Special Event Trigger. See Compare (ECCP/CCP Modules). Special Features of the CPU ........................................... 235 Special Function Registers ................................................ 61 Map ............................................................................ 61 SPI Mode (MSSP) Associated Registers ............................................... 158 Bus Mode Compatibility ........................................... 157 Clock Speed and Module Interactions ..................... 157 Effects of a Reset .................................................... 157 Enabling SPI I/O ...................................................... 153 Master Mode ............................................................ 154 Master/Slave Connection ........................................ 153 Operation ................................................................. 152 Operation in Power-Managed Modes ...................... 157 Serial Clock ............................................................. 149 Serial Data In ........................................................... 149 Serial Data Out ........................................................ 149 Slave Mode .............................................................. 155 Slave Select ............................................................. 149 Slave Select Synchronization .................................. 155 SPI Clock ................................................................. 154 Typical Connection .................................................. 153 SSPOV ............................................................................ 182 SSPOV Status Flag ......................................................... 182 SSPxSTAT Register R/W Bit ............................................................ 164, 166 SSx .................................................................................. 149 Stack Full/Underflow Resets .............................................. 55 STATUS Register .............................................................. 65 SUBFSR .......................................................................... 295 SUBFWB ......................................................................... 284 SUBLW ............................................................................ 285 SUBULNK ........................................................................ 295 SUBWF ............................................................................ 285 SUBWFB ......................................................................... 286 SWAPF ............................................................................ 286
T
Table Pointer Operations (table) ........................................ 74 Table Reads/Table Writes ................................................. 55 TBLRD ............................................................................. 287 TBLWT ............................................................................ 288
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Timer0 .............................................................................. 115 Associated Registers ............................................... 117 Clock Source Select (T0CS Bit) ............................... 116 Operation ................................................................. 116 Overflow Interrupt .................................................... 117 Prescaler .................................................................. 117 Prescaler Assignment (PSA Bit) .............................. 117 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 117 Prescaler. See Prescaler, Timer0. Reads and Writes in 16-Bit Mode ............................ 116 Source Edge Select (T0SE Bit) ................................ 116 Switching Prescaler Assignment .............................. 117 Timer1 .............................................................................. 119 16-Bit Read/Write Mode ........................................... 121 Associated Registers ............................................... 124 Interrupt .................................................................... 122 Operation ................................................................. 120 Oscillator .......................................................... 119, 121 Layout Considerations ..................................... 122 Oscillator, as Secondary Clock .................................. 30 Overflow Interrupt .................................................... 119 Resetting, Using the ECCP/CCP Special Event Trigger ....................................... 123 Special Event Trigger (ECCP) ................................. 136 TMR1H Register ...................................................... 119 TMR1L Register ....................................................... 119 Use as a Clock Source ............................................ 122 Use as a Real-Time Clock ....................................... 123 Timer2 .............................................................................. 125 Associated Registers ............................................... 126 Interrupt .................................................................... 126 Operation ................................................................. 125 Output ...................................................................... 126 PR2 Register .................................................... 132, 137 TMR2-to-PR2 Match Interrupt .......................... 132, 137 Timing Diagrams A/D Conversion ........................................................ 334 Acknowledge Sequence .......................................... 185 Asynchronous Reception ......................................... 206 Asynchronous Transmission .................................... 204 Asynchronous Transmission (Back to Back) ........... 204 Automatic Baud Rate Calculation ............................ 202 Auto-Wake-up Bit (WUE) During Normal Operation ............................................. 207 Auto-Wake-up Bit (WUE) During Sleep ................... 207 Baud Rate Generator with Clock Arbitration ............ 179 BRG Overflow Sequence ......................................... 202 BRG Reset Due to SDAx Arbitration During Start Condition ................................................. 189 Brown-out Reset (BOR) ........................................... 322 Bus Collision During a Repeated Start Condition (Case 1) .................................. 190 Bus Collision During a Repeated Start Condition (Case 2) .................................. 190 Bus Collision During a Start Condition (SCLx = 0) ............................... 189 Bus Collision During a Stop Condition (Case 1) ................................... 191 Bus Collision During a Stop Condition (Case 2) ................................... 191 Bus Collision During Start Condition (SDAx Only) ............................ 188 Bus Collision for Transmit and Acknowledge ........... 187 Capture/Compare/PWM (Including ECCP Module) ................................ 324 CLKO and I/O .......................................................... 321 Clock Synchronization ............................................. 172 Clock/Instruction Cycle .............................................. 56 EUSART Synchronous Receive (Master/Slave) ...... 333 EUSART Synchronous Transmission (Master/Slave) ................................................. 333 Example SPI Master Mode (CKE = 0) ..................... 325 Example SPI Master Mode (CKE = 1) ..................... 326 Example SPI Slave Mode (CKE = 0) ....................... 327 Example SPI Slave Mode (CKE = 1) ....................... 328 External Clock (All Modes Except PLL) ................... 319 Fail-Safe Clock Monitor ........................................... 246 First Start Bit Timing ................................................ 180 Full-Bridge PWM Output .......................................... 141 Half-Bridge PWM Output ......................................... 140 I2C Bus Data ............................................................ 329 I2C Bus Start/Stop Bits ............................................ 329 I2C Master Mode (7 or 10-Bit Transmission) ........... 183 I2C Master Mode (7-Bit Reception) .......................... 184 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 169 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 174 I2C Slave Mode (10-Bit Transmission) .................... 170 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 167 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 173 I2C Slave Mode (7-Bit Transmission) ...................... 168 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 175 I2C Stop Condition Receive or Transmit Mode ........ 186 Master SSP I2C Bus Data ........................................ 331 Master SSP I2C Bus Start/Stop Bits ........................ 331 Parallel Slave Port (PSP) Read ............................... 114 Parallel Slave Port (PSP) Write ............................... 114 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 146 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 146 PWM Direction Change ........................................... 143 PWM Direction Change at Near 100% Duty Cycle ............................................. 143 PWM Output ............................................................ 132 Repeated Start Condition ........................................ 181 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 322 Send Break Character Sequence ............................ 208 Slave Synchronization ............................................. 155 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 45 SPI Mode (Master Mode) ......................................... 154 SPI Mode (Slave Mode, CKE = 0) ........................... 156 SPI Mode (Slave Mode, CKE = 1) ........................... 156 Synchronous Reception (Master Mode, SREN) ..................................... 211 Synchronous Transmission ..................................... 209 Synchronous Transmission (Through TXEN) .......... 210 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ...................... 45 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ...................... 45 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise /Tpwrt) ............... 44 Timer0 and Timer1 External Clock .......................... 323 Transition for Entry to Idle Mode ................................ 39 Transition for Entry to SEC_RUN Mode .................... 36 Transition for Entry to Sleep Mode ............................ 38 Transition for Two-Speed Start-up (INTRC) ............ 244
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Transition for Wake From Idle to Run Mode .............. 39 Transition for Wake From Sleep ................................ 38 Transition From RC_RUN Mode to PRI_RUN Mode ................................................. 37 Transition to RC_RUN Mode ..................................... 37 Timing Diagrams and Specifications A/D Conversion Requirements ................................ 335 AC Characteristics Internal RC Accuracy ....................................... 320 Capture/Compare/PWM Requirements (Including ECCP Module) ................................ 324 CLKO and I/O Requirements ................................... 321 EUSART Synchronous Receive Requirements .................................................. 333 EUSART Synchronous Transmission Requirements .................................................. 333 Example SPI Mode Requirements (CKE = 0) ................................................. 325, 327 Example SPI Mode Requirements (CKE = 1) ......................................................... 326 Example SPI Slave Mode Requirements (CKE = 1) 328 External Clock Requirements .................................. 319 I2C Bus Data Requirements (Slave Mode) .............. 330 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 329 Master SSP I2C Bus Data Requirements ................ 332 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 331 Parallel Slave Port Requirements ............................ 324 PLL Clock ................................................................. 320 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................ 322 Timer0 and Timer1 External Clock Requirements .................................................. 323 Top-of-Stack Access .......................................................... 53 TRISE Register PSPMODE Bit .......................................................... 107 TSTFSZ ........................................................................... 289 Two-Speed Start-up ................................................. 235, 244 Two-Word Instructions Example Cases .......................................................... 57 TXSTA Register BRGH Bit ................................................................. 197
V
Voltage Reference Specifications .................................... 316 Voltage Regulator (On-Chip) ........................................... 243
W
Watchdog Timer (WDT) ........................................... 235, 242 Associated Registers ............................................... 242 Control Register ....................................................... 242 During Oscillator Failure .......................................... 245 Programming Considerations .................................. 242 WCOL ...................................................... 180, 181, 182, 185 WCOL Status Flag ................................... 180, 181, 182, 185 WWW Address ................................................................ 363 WWW, On-Line Support ...................................................... 6
X
XORLW ........................................................................... 289 XORWF ........................................................................... 290
(c) 2009 Microchip Technology Inc.
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NOTES:
DS39682E-page 362
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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PIC18F45J10 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39682E FAX: (______) _________ - _________
Device: PIC18F45J10 Family Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39682E-page 364
(c) 2009 Microchip Technology Inc.
PIC18F45J10 FAMILY
PIC18F45J10 FAMILY PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) c) PIC18LF45J10-I/P 301 = Industrial temp., PDIP package, QTP pattern #301. PIC18LF24J10-I/SO = Industrial temp., SOIC package. PIC18LF44J10-I/P = Industrial temp., PDIP package.
Device
PIC18F24J10/25J10, PIC18F44J10/45J10, PIC18F24J10/25J10T(1), PIC18F44J10/45J10T(1); VDD range 2.7V to 3.6V PIC18LF24J10/25J10, PIC18LF44J10/45J10, PIC18LF24J10/25J10T(1), PIC18LF44J10/45J10T(1); VDDCORE range 2.0V to 2.7V I PT SO SP P ML SS = = = = = = = -40C to +85C (Industrial) TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP PDIP QFN SSOP
Temperature Range Package
Note 1:
T
= in tape and reel TQFP packages only.
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
(c) 2009 Microchip Technology Inc.
DS39682E-page 365
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
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EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS39682E-page 366
(c) 2009 Microchip Technology Inc.

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